Reliability Guard Band Reduction by Differential Targeting of pMOS Gate Oxide Thickness
In the presented work we demonstrate an efficient way to improve the balance between performance and reliability in the case that microprocessor speed is limited by a pMOS dominated speed path. It is shown that with differential targeted, thicker pMOS gate oxide thickness (TOX), realized by the sele...
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| creator | Geilenkeuser, R. Wieczorek, K. Trentzsch, M. Graetsch, F. Bayha, B. Samohvalov, V. Paetzold, T. Schink, T. |
| description | In the presented work we demonstrate an efficient way to improve the balance between performance and reliability in the case that microprocessor speed is limited by a pMOS dominated speed path. It is shown that with differential targeted, thicker pMOS gate oxide thickness (TOX), realized by the selective control of nMOS and pMOS GOX, pMOS degradation in terms of HCI and NBTI can be effectively reduced at tolerable loss of initial product frequency. Fast Wafer Level Reliability (fWLR) techniques are used as an effective tool to quickly characterize the thickness dependence of the degradation components. Product wearout experiments confirm that less product frequency degradation is observed with a thicker P-TOX, which is in agreement with the degradation of ringoscillator frequency as well, stressed in parallel to the product. |
| doi_str_mv | 10.1109/IRWS.2008.4796096 |
| format | Conference Proceeding |
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It is shown that with differential targeted, thicker pMOS gate oxide thickness (TOX), realized by the selective control of nMOS and pMOS GOX, pMOS degradation in terms of HCI and NBTI can be effectively reduced at tolerable loss of initial product frequency. Fast Wafer Level Reliability (fWLR) techniques are used as an effective tool to quickly characterize the thickness dependence of the degradation components. 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Product wearout experiments confirm that less product frequency degradation is observed with a thicker P-TOX, which is in agreement with the degradation of ringoscillator frequency as well, stressed in parallel to the product.</description><subject>Degradation</subject><subject>Frequency</subject><subject>Human computer interaction</subject><subject>Microprocessors</subject><subject>MOS devices</subject><subject>Niobium compounds</subject><subject>Stress</subject><subject>Testing</subject><subject>Titanium compounds</subject><subject>Voltage</subject><issn>1930-8841</issn><issn>2374-8036</issn><isbn>9781424421947</isbn><isbn>1424421942</isbn><isbn>9781424421954</isbn><isbn>1424421950</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2008</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpVkM1Kw0AURsc_sNY-gLiZF0i9M3OTmVlqq7VQCbSBLstM5qaOxrQkKdi3V7AbV9-BA2fxMXYnYCwE2If5cr0aSwAzRm0zsNkZG1ltBEpEKWyK52wglcbEgMou_jnUl2wgrILEGBTX7KbrPgAkCGUGbL2kOjof69gf-ezg2sCfXBP4ksKh7OOu4f7Ip7GqqKWmj67mhWu31Mdmy3cV37_lKz5zPfH8OwbixXssPxvqult2Vbm6o9Fph6x4eS4mr8kin80nj4skCp32CSmFWgRNLqWUlA9QlhmKYIgAbKDKki8JUzQpGY8yyEqqkrzPPOAvDtn9XzYS0Wbfxi_XHjeni9QPLd5Wyg</recordid><startdate>200810</startdate><enddate>200810</enddate><creator>Geilenkeuser, R.</creator><creator>Wieczorek, K.</creator><creator>Trentzsch, M.</creator><creator>Graetsch, F.</creator><creator>Bayha, B.</creator><creator>Samohvalov, V.</creator><creator>Paetzold, T.</creator><creator>Schink, T.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200810</creationdate><title>Reliability Guard Band Reduction by Differential Targeting of pMOS Gate Oxide Thickness</title><author>Geilenkeuser, R. ; Wieczorek, K. ; Trentzsch, M. ; Graetsch, F. ; Bayha, B. ; Samohvalov, V. ; Paetzold, T. ; Schink, T.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-e33471d7ea5e5e3bd0cc641d8ee009def9ebce45485e8b42d2f23cebb6b04f23</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2008</creationdate><topic>Degradation</topic><topic>Frequency</topic><topic>Human computer interaction</topic><topic>Microprocessors</topic><topic>MOS devices</topic><topic>Niobium compounds</topic><topic>Stress</topic><topic>Testing</topic><topic>Titanium compounds</topic><topic>Voltage</topic><toplevel>online_resources</toplevel><creatorcontrib>Geilenkeuser, R.</creatorcontrib><creatorcontrib>Wieczorek, K.</creatorcontrib><creatorcontrib>Trentzsch, M.</creatorcontrib><creatorcontrib>Graetsch, F.</creatorcontrib><creatorcontrib>Bayha, B.</creatorcontrib><creatorcontrib>Samohvalov, V.</creatorcontrib><creatorcontrib>Paetzold, T.</creatorcontrib><creatorcontrib>Schink, T.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Geilenkeuser, R.</au><au>Wieczorek, K.</au><au>Trentzsch, M.</au><au>Graetsch, F.</au><au>Bayha, B.</au><au>Samohvalov, V.</au><au>Paetzold, T.</au><au>Schink, T.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Reliability Guard Band Reduction by Differential Targeting of pMOS Gate Oxide Thickness</atitle><btitle>2008 IEEE International Integrated Reliability Workshop Final Report</btitle><stitle>IRWS</stitle><date>2008-10</date><risdate>2008</risdate><spage>100</spage><epage>104</epage><pages>100-104</pages><issn>1930-8841</issn><eissn>2374-8036</eissn><isbn>9781424421947</isbn><isbn>1424421942</isbn><eisbn>9781424421954</eisbn><eisbn>1424421950</eisbn><abstract>In the presented work we demonstrate an efficient way to improve the balance between performance and reliability in the case that microprocessor speed is limited by a pMOS dominated speed path. It is shown that with differential targeted, thicker pMOS gate oxide thickness (TOX), realized by the selective control of nMOS and pMOS GOX, pMOS degradation in terms of HCI and NBTI can be effectively reduced at tolerable loss of initial product frequency. Fast Wafer Level Reliability (fWLR) techniques are used as an effective tool to quickly characterize the thickness dependence of the degradation components. Product wearout experiments confirm that less product frequency degradation is observed with a thicker P-TOX, which is in agreement with the degradation of ringoscillator frequency as well, stressed in parallel to the product.</abstract><pub>IEEE</pub><doi>10.1109/IRWS.2008.4796096</doi><tpages>5</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 1930-8841 |
| ispartof | 2008 IEEE International Integrated Reliability Workshop Final Report, 2008, p.100-104 |
| issn | 1930-8841 2374-8036 |
| language | eng |
| recordid | cdi_ieee_primary_4796096 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Degradation Frequency Human computer interaction Microprocessors MOS devices Niobium compounds Stress Testing Titanium compounds Voltage |
| title | Reliability Guard Band Reduction by Differential Targeting of pMOS Gate Oxide Thickness |
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