Investigation of stack as a low power design technique for 6-T SRAM cell

Low power large scale integration of memory technology is an increasing important and growing area of electronics. In nano-scaled devices, standby power needs to be reduced effectively for high performance System on Chip designs. As per the dasiaInternational Technology of Roadmap for Semiconductors-2007psila, high leakage current in nanometer regime is becoming a significant portion of power dissipation in cmos circuits as threshold voltage, channel length and gate oxide thickness are scaled. This paper explores the possibility of reduction in the energy dissipation in 6T-SRAM cell. This paper evaluates SRAM cell with and without introducing stacking in nanometer regime. Overall leakage in a stack of transistors reduces due to modification of gate to source voltage, threshold voltage and drain induced barrier lowering. T-spice and L-Edit simulation results shows that compared to the conventional high performance SRAM cells, stacked cells offer significant reduction of power consumption. Some of the issue like static noise margin, increase in level of stack and variation in length are discussed in the paper.