A low power high speed ROIC design for 1024×1024 IRFPA with novel readout stage
A low power high speed Read-Out Integrated Circuit (ROIC) for a short-wave Infra-Red Focal Plane Array (IRFPA) is designed as a prototype for 1024 times 1024 image system. Ripple integration and readout scheme as well as highly efficient power management are introduced to this design in order to dec...
Gespeichert in:
| Hauptverfasser: | , , , , |
|---|---|
| Format: | Tagungsbericht |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 4 |
|---|---|
| container_issue | |
| container_start_page | 1 |
| container_title | |
| container_volume | |
| creator | Chang Liu Wengao Lu Zhongjian Chen Haimei Bian Lijiu Ji |
| description | A low power high speed Read-Out Integrated Circuit (ROIC) for a short-wave Infra-Red Focal Plane Array (IRFPA) is designed as a prototype for 1024 times 1024 image system. Ripple integration and readout scheme as well as highly efficient power management are introduced to this design in order to decrease total power. To further increase the readout speed while decrease the power dissipation, a novel readout stage is proposed and adopted in this circuit. By using the new structure, the ROIC achieves a data rate of 10 M/s per channel, with the total power dissipation of 56 mW. |
| doi_str_mv | 10.1109/EDSSC.2008.4760710 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_4760710</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>4760710</ieee_id><sourcerecordid>4760710</sourcerecordid><originalsourceid>FETCH-LOGICAL-i90t-57ed4ec43b5b059f83e08fbc122296fc6df34aabd6b947ec904004af39ac088a3</originalsourceid><addsrcrecordid>eNotUNtOg0AUXGOaaCs_oC_7A-DZG7CPDbaVpElN2_dmgbOwBgsBlPglfpA_Jo09DzOZZGYyOYQ8MggYA_28ejkckoADxIGMQogY3BBPRzGTXEquJPBbMr8KodWMzC9eDZIJfke8vn-H6aQSSof35G1J62akbTNiRytXVrRvEQu636UJLbB35ZnapqMMuPz9uSBN9-spNbqhoufmC2vaoSmaz4H2gynxgcysqXv0rrwgx_XqmLz6290mTZZb32kYfBVhITGXIlMZKG1jgRDbLGeccx3aPCyskMZkRZhpGWE-zZ82Gyu0ySGOjViQp_9ah4intnMfpvs-XR8i_gAg-1A5</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>A low power high speed ROIC design for 1024×1024 IRFPA with novel readout stage</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Chang Liu ; Wengao Lu ; Zhongjian Chen ; Haimei Bian ; Lijiu Ji</creator><creatorcontrib>Chang Liu ; Wengao Lu ; Zhongjian Chen ; Haimei Bian ; Lijiu Ji</creatorcontrib><description>A low power high speed Read-Out Integrated Circuit (ROIC) for a short-wave Infra-Red Focal Plane Array (IRFPA) is designed as a prototype for 1024 times 1024 image system. Ripple integration and readout scheme as well as highly efficient power management are introduced to this design in order to decrease total power. To further increase the readout speed while decrease the power dissipation, a novel readout stage is proposed and adopted in this circuit. By using the new structure, the ROIC achieves a data rate of 10 M/s per channel, with the total power dissipation of 56 mW.</description><identifier>ISBN: 1424425395</identifier><identifier>ISBN: 9781424425396</identifier><identifier>EISBN: 9781424425402</identifier><identifier>EISBN: 1424425409</identifier><identifier>DOI: 10.1109/EDSSC.2008.4760710</identifier><identifier>LCCN: 2008904132</identifier><language>eng</language><publisher>IEEE</publisher><subject>Capacitors ; CMOS logic circuits ; Cooling ; Detectors ; Logic arrays ; Logic devices ; Power amplifiers ; Power dissipation ; Prototypes ; Timing</subject><ispartof>2008 IEEE International Conference on Electron Devices and Solid-State Circuits, 2008, p.1-4</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4760710$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4760710$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Chang Liu</creatorcontrib><creatorcontrib>Wengao Lu</creatorcontrib><creatorcontrib>Zhongjian Chen</creatorcontrib><creatorcontrib>Haimei Bian</creatorcontrib><creatorcontrib>Lijiu Ji</creatorcontrib><title>A low power high speed ROIC design for 1024×1024 IRFPA with novel readout stage</title><title>2008 IEEE International Conference on Electron Devices and Solid-State Circuits</title><addtitle>EDSSC</addtitle><description>A low power high speed Read-Out Integrated Circuit (ROIC) for a short-wave Infra-Red Focal Plane Array (IRFPA) is designed as a prototype for 1024 times 1024 image system. Ripple integration and readout scheme as well as highly efficient power management are introduced to this design in order to decrease total power. To further increase the readout speed while decrease the power dissipation, a novel readout stage is proposed and adopted in this circuit. By using the new structure, the ROIC achieves a data rate of 10 M/s per channel, with the total power dissipation of 56 mW.</description><subject>Capacitors</subject><subject>CMOS logic circuits</subject><subject>Cooling</subject><subject>Detectors</subject><subject>Logic arrays</subject><subject>Logic devices</subject><subject>Power amplifiers</subject><subject>Power dissipation</subject><subject>Prototypes</subject><subject>Timing</subject><isbn>1424425395</isbn><isbn>9781424425396</isbn><isbn>9781424425402</isbn><isbn>1424425409</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2008</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotUNtOg0AUXGOaaCs_oC_7A-DZG7CPDbaVpElN2_dmgbOwBgsBlPglfpA_Jo09DzOZZGYyOYQ8MggYA_28ejkckoADxIGMQogY3BBPRzGTXEquJPBbMr8KodWMzC9eDZIJfke8vn-H6aQSSof35G1J62akbTNiRytXVrRvEQu636UJLbB35ZnapqMMuPz9uSBN9-spNbqhoufmC2vaoSmaz4H2gynxgcysqXv0rrwgx_XqmLz6290mTZZb32kYfBVhITGXIlMZKG1jgRDbLGeccx3aPCyskMZkRZhpGWE-zZ82Gyu0ySGOjViQp_9ah4intnMfpvs-XR8i_gAg-1A5</recordid><startdate>200812</startdate><enddate>200812</enddate><creator>Chang Liu</creator><creator>Wengao Lu</creator><creator>Zhongjian Chen</creator><creator>Haimei Bian</creator><creator>Lijiu Ji</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200812</creationdate><title>A low power high speed ROIC design for 1024×1024 IRFPA with novel readout stage</title><author>Chang Liu ; Wengao Lu ; Zhongjian Chen ; Haimei Bian ; Lijiu Ji</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-57ed4ec43b5b059f83e08fbc122296fc6df34aabd6b947ec904004af39ac088a3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2008</creationdate><topic>Capacitors</topic><topic>CMOS logic circuits</topic><topic>Cooling</topic><topic>Detectors</topic><topic>Logic arrays</topic><topic>Logic devices</topic><topic>Power amplifiers</topic><topic>Power dissipation</topic><topic>Prototypes</topic><topic>Timing</topic><toplevel>online_resources</toplevel><creatorcontrib>Chang Liu</creatorcontrib><creatorcontrib>Wengao Lu</creatorcontrib><creatorcontrib>Zhongjian Chen</creatorcontrib><creatorcontrib>Haimei Bian</creatorcontrib><creatorcontrib>Lijiu Ji</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Chang Liu</au><au>Wengao Lu</au><au>Zhongjian Chen</au><au>Haimei Bian</au><au>Lijiu Ji</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A low power high speed ROIC design for 1024×1024 IRFPA with novel readout stage</atitle><btitle>2008 IEEE International Conference on Electron Devices and Solid-State Circuits</btitle><stitle>EDSSC</stitle><date>2008-12</date><risdate>2008</risdate><spage>1</spage><epage>4</epage><pages>1-4</pages><isbn>1424425395</isbn><isbn>9781424425396</isbn><eisbn>9781424425402</eisbn><eisbn>1424425409</eisbn><abstract>A low power high speed Read-Out Integrated Circuit (ROIC) for a short-wave Infra-Red Focal Plane Array (IRFPA) is designed as a prototype for 1024 times 1024 image system. Ripple integration and readout scheme as well as highly efficient power management are introduced to this design in order to decrease total power. To further increase the readout speed while decrease the power dissipation, a novel readout stage is proposed and adopted in this circuit. By using the new structure, the ROIC achieves a data rate of 10 M/s per channel, with the total power dissipation of 56 mW.</abstract><pub>IEEE</pub><doi>10.1109/EDSSC.2008.4760710</doi><tpages>4</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISBN: 1424425395 |
| ispartof | 2008 IEEE International Conference on Electron Devices and Solid-State Circuits, 2008, p.1-4 |
| issn | |
| language | eng |
| recordid | cdi_ieee_primary_4760710 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Capacitors CMOS logic circuits Cooling Detectors Logic arrays Logic devices Power amplifiers Power dissipation Prototypes Timing |
| title | A low power high speed ROIC design for 1024×1024 IRFPA with novel readout stage |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-23T03%3A04%3A47IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=A%20low%20power%20high%20speed%20ROIC%20design%20for%201024%C3%971024%20IRFPA%20with%20novel%20readout%20stage&rft.btitle=2008%20IEEE%20International%20Conference%20on%20Electron%20Devices%20and%20Solid-State%20Circuits&rft.au=Chang%20Liu&rft.date=2008-12&rft.spage=1&rft.epage=4&rft.pages=1-4&rft.isbn=1424425395&rft.isbn_list=9781424425396&rft_id=info:doi/10.1109/EDSSC.2008.4760710&rft_dat=%3Cieee_6IE%3E4760710%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=9781424425402&rft.eisbn_list=1424425409&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=4760710&rfr_iscdi=true |