An experimental 295 MHz CMOS 4K/spl times/256 SRAM using bidirectional read/write shared sense amps and self-timed pulsed word-line drivers

An experimental 4 K word by 256 b CMOS synchronous SRAM employing read/write shared sense amplifiers and self-timed pulsed word-lines is described. The read/write shared sense amplifier allows the RAM to have 256 I/Os and the self-timed pulsed word-line scheme reduces power consumption. Fully differ...

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Veröffentlicht in:	IEEE journal of solid-state circuits 1995-11, Vol.30 (11), p.1286-1290
Hauptverfasser:	Kushiyama, N., Tan, C., Clark, R., Lin, J., Perner, F., Martin, L., Leonard, M., Coussens, G., Cham, K.
Format:	Artikel
Sprache:	eng
Schlagworte:	Bandwidth Circuits Clocks CMOS process Companies Decoding Laboratories Pipelines Pulse amplifiers Random access memory
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