Error floor analysis for an ensemble of easily implementable irregular (2048, 1024) LDPC codes

The following paper describes a design process for constructing semirandom LDPC codes with characteristics that are suitable for a relatively simple implementation for both the encoding and decoding operation. The paper will focus on two particular code ensembles - both rate-1/2 (2048, 1024) designs...

Ausführliche Beschreibung

Bibliographische Detailangaben

1. Verfasser:	Cole, C.A.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Algorithm design and analysis Bit error rate Encoding Error analysis error floors Floors irregular designs Iterative algorithms Iterative decoding LDPC Message passing Parity check codes Process design
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