Error floor analysis for an ensemble of easily implementable irregular (2048, 1024) LDPC codes
The following paper describes a design process for constructing semirandom LDPC codes with characteristics that are suitable for a relatively simple implementation for both the encoding and decoding operation. The paper will focus on two particular code ensembles - both rate-1/2 (2048, 1024) designs...
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| creator | Cole, C.A. |
| description | The following paper describes a design process for constructing semirandom LDPC codes with characteristics that are suitable for a relatively simple implementation for both the encoding and decoding operation. The paper will focus on two particular code ensembles - both rate-1/2 (2048, 1024) designs with a specified irregular degree distribution. These code parameters were chosen simply because they satisfied a project design constraint, but the process described can be extended to most other low-density designs. Some new insights into the codepsilas performance curve behavior in the low error region under message passing decoding are presented. |
| doi_str_mv | 10.1109/MILCOM.2008.4753229 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_4753229</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>4753229</ieee_id><sourcerecordid>4753229</sourcerecordid><originalsourceid>FETCH-LOGICAL-i90t-7f5c96533037983b0a776f43963711656442b7c7f5ad80dea6584007848e69883</originalsourceid><addsrcrecordid>eNpVUMtOAkEQHB8kIvIFXOaoiYs975mjWVFJluCBs2SAXjNmliUzeODvXZSYWIfuVFWnki5CRgzGjIF7mE2rcj4bcwA7lkYJzt0ZGTpjmeRScm2MOid9zpQqjLL64p-n7eWfZ2yPXB9jHCil-BUZ5vwJHaRijMk-eZ-k1CZax7abfuvjIYdM6x9CcZuxWUWkbU3R5xAPNDS7iA1u9_6oh5Tw4yv6RG85SHtPGXB5R6unt5Ku2w3mG9Krfcw4PO0BWTxPFuVrUc1fpuVjVQQH-8LUau20EgKEcVaswBujaymcFoYxrXT318qsuzO_sbBBr5WVAMZKi9pZKwZk9BsbEHG5S6Hx6bA8NSe-AYuMV_U</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Error floor analysis for an ensemble of easily implementable irregular (2048, 1024) LDPC codes</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Cole, C.A.</creator><creatorcontrib>Cole, C.A.</creatorcontrib><description>The following paper describes a design process for constructing semirandom LDPC codes with characteristics that are suitable for a relatively simple implementation for both the encoding and decoding operation. The paper will focus on two particular code ensembles - both rate-1/2 (2048, 1024) designs with a specified irregular degree distribution. These code parameters were chosen simply because they satisfied a project design constraint, but the process described can be extended to most other low-density designs. Some new insights into the codepsilas performance curve behavior in the low error region under message passing decoding are presented.</description><identifier>ISSN: 2155-7578</identifier><identifier>ISBN: 9781424426768</identifier><identifier>ISBN: 1424426766</identifier><identifier>EISSN: 2155-7586</identifier><identifier>EISBN: 9781424426775</identifier><identifier>EISBN: 1424426774</identifier><identifier>DOI: 10.1109/MILCOM.2008.4753229</identifier><identifier>LCCN: 2008905552</identifier><language>eng</language><publisher>IEEE</publisher><subject>Algorithm design and analysis ; Bit error rate ; Encoding ; Error analysis ; error floors ; Floors ; irregular designs ; Iterative algorithms ; Iterative decoding ; LDPC ; Message passing ; Parity check codes ; Process design</subject><ispartof>MILCOM 2008 - 2008 IEEE Military Communications Conference, 2008, p.1-5</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4753229$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,777,781,786,787,2052,27906,54901</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4753229$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Cole, C.A.</creatorcontrib><title>Error floor analysis for an ensemble of easily implementable irregular (2048, 1024) LDPC codes</title><title>MILCOM 2008 - 2008 IEEE Military Communications Conference</title><addtitle>MILCOM</addtitle><description>The following paper describes a design process for constructing semirandom LDPC codes with characteristics that are suitable for a relatively simple implementation for both the encoding and decoding operation. The paper will focus on two particular code ensembles - both rate-1/2 (2048, 1024) designs with a specified irregular degree distribution. These code parameters were chosen simply because they satisfied a project design constraint, but the process described can be extended to most other low-density designs. Some new insights into the codepsilas performance curve behavior in the low error region under message passing decoding are presented.</description><subject>Algorithm design and analysis</subject><subject>Bit error rate</subject><subject>Encoding</subject><subject>Error analysis</subject><subject>error floors</subject><subject>Floors</subject><subject>irregular designs</subject><subject>Iterative algorithms</subject><subject>Iterative decoding</subject><subject>LDPC</subject><subject>Message passing</subject><subject>Parity check codes</subject><subject>Process design</subject><issn>2155-7578</issn><issn>2155-7586</issn><isbn>9781424426768</isbn><isbn>1424426766</isbn><isbn>9781424426775</isbn><isbn>1424426774</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2008</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpVUMtOAkEQHB8kIvIFXOaoiYs975mjWVFJluCBs2SAXjNmliUzeODvXZSYWIfuVFWnki5CRgzGjIF7mE2rcj4bcwA7lkYJzt0ZGTpjmeRScm2MOid9zpQqjLL64p-n7eWfZ2yPXB9jHCil-BUZ5vwJHaRijMk-eZ-k1CZax7abfuvjIYdM6x9CcZuxWUWkbU3R5xAPNDS7iA1u9_6oh5Tw4yv6RG85SHtPGXB5R6unt5Ku2w3mG9Krfcw4PO0BWTxPFuVrUc1fpuVjVQQH-8LUau20EgKEcVaswBujaymcFoYxrXT318qsuzO_sbBBr5WVAMZKi9pZKwZk9BsbEHG5S6Hx6bA8NSe-AYuMV_U</recordid><startdate>200811</startdate><enddate>200811</enddate><creator>Cole, C.A.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>200811</creationdate><title>Error floor analysis for an ensemble of easily implementable irregular (2048, 1024) LDPC codes</title><author>Cole, C.A.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-7f5c96533037983b0a776f43963711656442b7c7f5ad80dea6584007848e69883</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2008</creationdate><topic>Algorithm design and analysis</topic><topic>Bit error rate</topic><topic>Encoding</topic><topic>Error analysis</topic><topic>error floors</topic><topic>Floors</topic><topic>irregular designs</topic><topic>Iterative algorithms</topic><topic>Iterative decoding</topic><topic>LDPC</topic><topic>Message passing</topic><topic>Parity check codes</topic><topic>Process design</topic><toplevel>online_resources</toplevel><creatorcontrib>Cole, C.A.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Cole, C.A.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Error floor analysis for an ensemble of easily implementable irregular (2048, 1024) LDPC codes</atitle><btitle>MILCOM 2008 - 2008 IEEE Military Communications Conference</btitle><stitle>MILCOM</stitle><date>2008-11</date><risdate>2008</risdate><spage>1</spage><epage>5</epage><pages>1-5</pages><issn>2155-7578</issn><eissn>2155-7586</eissn><isbn>9781424426768</isbn><isbn>1424426766</isbn><eisbn>9781424426775</eisbn><eisbn>1424426774</eisbn><abstract>The following paper describes a design process for constructing semirandom LDPC codes with characteristics that are suitable for a relatively simple implementation for both the encoding and decoding operation. The paper will focus on two particular code ensembles - both rate-1/2 (2048, 1024) designs with a specified irregular degree distribution. These code parameters were chosen simply because they satisfied a project design constraint, but the process described can be extended to most other low-density designs. Some new insights into the codepsilas performance curve behavior in the low error region under message passing decoding are presented.</abstract><pub>IEEE</pub><doi>10.1109/MILCOM.2008.4753229</doi><tpages>5</tpages></addata></record> |
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| identifier | ISSN: 2155-7578 |
| ispartof | MILCOM 2008 - 2008 IEEE Military Communications Conference, 2008, p.1-5 |
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| language | eng |
| recordid | cdi_ieee_primary_4753229 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Algorithm design and analysis Bit error rate Encoding Error analysis error floors Floors irregular designs Iterative algorithms Iterative decoding LDPC Message passing Parity check codes Process design |
| title | Error floor analysis for an ensemble of easily implementable irregular (2048, 1024) LDPC codes |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-18T10%3A18%3A59IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Error%20floor%20analysis%20for%20an%20ensemble%20of%20easily%20implementable%20irregular%20(2048,%201024)%20LDPC%20codes&rft.btitle=MILCOM%202008%20-%202008%20IEEE%20Military%20Communications%20Conference&rft.au=Cole,%20C.A.&rft.date=2008-11&rft.spage=1&rft.epage=5&rft.pages=1-5&rft.issn=2155-7578&rft.eissn=2155-7586&rft.isbn=9781424426768&rft.isbn_list=1424426766&rft_id=info:doi/10.1109/MILCOM.2008.4753229&rft_dat=%3Cieee_6IE%3E4753229%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=9781424426775&rft.eisbn_list=1424426774&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=4753229&rfr_iscdi=true |