Ring data location prediction scheme for Non-Uniform Cache Architectures
Increases in cache capacity are accompanied by growing wire delays due to technology scaling. Non-uniform cache architecture (NUCA) is one of proposed solutions to reducing the average access latency in such cache designs. While most of the prior NUCA work focuses on data placement, data replacement...
Gespeichert in:
Hauptverfasser: | , , , , , |
---|---|
Format: | Tagungsbericht |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | 698 |
---|---|
container_issue | |
container_start_page | 693 |
container_title | |
container_volume | |
creator | Akioka, S. Feihui Li Malkowski, K. Raghavan, P. Kandemir, M. Irwin, M.J. |
description | Increases in cache capacity are accompanied by growing wire delays due to technology scaling. Non-uniform cache architecture (NUCA) is one of proposed solutions to reducing the average access latency in such cache designs. While most of the prior NUCA work focuses on data placement, data replacement, and migration related issues, this paper studies the problem of data search (access) in NUCA. In our architecture we arrange sets of banks with equal access latency into rings. Our last access based (LAB) prediction scheme predicts the ring that is expected to contain the required data and checks the banks in that ring first for the data block sought. We compare our scheme to two alternate approaches: searching all rings in parallel, and searching rings sequentially. We show that our LAB ring prediction scheme reduces L2 energy significantly over the sequential and parallel schemes, while maintaining similar performance. Our LAB scheme reduces energy consumption by 15.9% relative to the sequential lookup scheme, and 53.8% relative to the parallel lookup scheme. |
doi_str_mv | 10.1109/ICCD.2008.4751936 |
format | Conference Proceeding |
fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_4751936</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>4751936</ieee_id><sourcerecordid>4751936</sourcerecordid><originalsourceid>FETCH-LOGICAL-i175t-8382ec81d4efccf6e9b7daff27614092b9df531595bd99f96c80c077a1d1d6c23</originalsourceid><addsrcrecordid>eNpVkMtKw0AYhccbGGsfQNzMCyTOP_dZllhtoSiIXZfJXOxIk5RJXPj2Bu3G1fk4B77FQegOSAVAzMO6rh8rSoiuuBJgmDxDc6M0cMo5lULzc1RQoWQpjZEX_zalLlEBRLJScsKv0c0wfJLJxEAVaPWWug_s7WjxoXd2TH2Hjzn45H5xcPvQBhz7jF_6rtx2acIW13bq8SK7fRqDG79yGG7RVbSHIcxPOUPbp-V7vSo3r8_rerEpEygxlpppGpwGz0N0LspgGuVtjFRJ4MTQxvgoGAgjGm9MNNJp4ohSFjx46Sibofs_bwoh7I45tTZ_706nsB_6ZlFk</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Ring data location prediction scheme for Non-Uniform Cache Architectures</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Akioka, S. ; Feihui Li ; Malkowski, K. ; Raghavan, P. ; Kandemir, M. ; Irwin, M.J.</creator><creatorcontrib>Akioka, S. ; Feihui Li ; Malkowski, K. ; Raghavan, P. ; Kandemir, M. ; Irwin, M.J.</creatorcontrib><description>Increases in cache capacity are accompanied by growing wire delays due to technology scaling. Non-uniform cache architecture (NUCA) is one of proposed solutions to reducing the average access latency in such cache designs. While most of the prior NUCA work focuses on data placement, data replacement, and migration related issues, this paper studies the problem of data search (access) in NUCA. In our architecture we arrange sets of banks with equal access latency into rings. Our last access based (LAB) prediction scheme predicts the ring that is expected to contain the required data and checks the banks in that ring first for the data block sought. We compare our scheme to two alternate approaches: searching all rings in parallel, and searching rings sequentially. We show that our LAB ring prediction scheme reduces L2 energy significantly over the sequential and parallel schemes, while maintaining similar performance. Our LAB scheme reduces energy consumption by 15.9% relative to the sequential lookup scheme, and 53.8% relative to the parallel lookup scheme.</description><identifier>ISSN: 1063-6404</identifier><identifier>ISBN: 9781424426577</identifier><identifier>ISBN: 142442657X</identifier><identifier>EISSN: 2576-6996</identifier><identifier>EISBN: 9781424426584</identifier><identifier>EISBN: 1424426588</identifier><identifier>DOI: 10.1109/ICCD.2008.4751936</identifier><language>eng</language><publisher>IEEE</publisher><subject>Costs ; Delay ; Energy consumption ; Hardware ; History ; Manufacturing processes ; Network-on-a-chip ; System-on-a-chip ; Topology ; Wire</subject><ispartof>2008 IEEE International Conference on Computer Design, 2008, p.693-698</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4751936$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2056,27923,54918</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4751936$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Akioka, S.</creatorcontrib><creatorcontrib>Feihui Li</creatorcontrib><creatorcontrib>Malkowski, K.</creatorcontrib><creatorcontrib>Raghavan, P.</creatorcontrib><creatorcontrib>Kandemir, M.</creatorcontrib><creatorcontrib>Irwin, M.J.</creatorcontrib><title>Ring data location prediction scheme for Non-Uniform Cache Architectures</title><title>2008 IEEE International Conference on Computer Design</title><addtitle>ICCD</addtitle><description>Increases in cache capacity are accompanied by growing wire delays due to technology scaling. Non-uniform cache architecture (NUCA) is one of proposed solutions to reducing the average access latency in such cache designs. While most of the prior NUCA work focuses on data placement, data replacement, and migration related issues, this paper studies the problem of data search (access) in NUCA. In our architecture we arrange sets of banks with equal access latency into rings. Our last access based (LAB) prediction scheme predicts the ring that is expected to contain the required data and checks the banks in that ring first for the data block sought. We compare our scheme to two alternate approaches: searching all rings in parallel, and searching rings sequentially. We show that our LAB ring prediction scheme reduces L2 energy significantly over the sequential and parallel schemes, while maintaining similar performance. Our LAB scheme reduces energy consumption by 15.9% relative to the sequential lookup scheme, and 53.8% relative to the parallel lookup scheme.</description><subject>Costs</subject><subject>Delay</subject><subject>Energy consumption</subject><subject>Hardware</subject><subject>History</subject><subject>Manufacturing processes</subject><subject>Network-on-a-chip</subject><subject>System-on-a-chip</subject><subject>Topology</subject><subject>Wire</subject><issn>1063-6404</issn><issn>2576-6996</issn><isbn>9781424426577</isbn><isbn>142442657X</isbn><isbn>9781424426584</isbn><isbn>1424426588</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2008</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpVkMtKw0AYhccbGGsfQNzMCyTOP_dZllhtoSiIXZfJXOxIk5RJXPj2Bu3G1fk4B77FQegOSAVAzMO6rh8rSoiuuBJgmDxDc6M0cMo5lULzc1RQoWQpjZEX_zalLlEBRLJScsKv0c0wfJLJxEAVaPWWug_s7WjxoXd2TH2Hjzn45H5xcPvQBhz7jF_6rtx2acIW13bq8SK7fRqDG79yGG7RVbSHIcxPOUPbp-V7vSo3r8_rerEpEygxlpppGpwGz0N0LspgGuVtjFRJ4MTQxvgoGAgjGm9MNNJp4ohSFjx46Sibofs_bwoh7I45tTZ_706nsB_6ZlFk</recordid><startdate>200810</startdate><enddate>200810</enddate><creator>Akioka, S.</creator><creator>Feihui Li</creator><creator>Malkowski, K.</creator><creator>Raghavan, P.</creator><creator>Kandemir, M.</creator><creator>Irwin, M.J.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>200810</creationdate><title>Ring data location prediction scheme for Non-Uniform Cache Architectures</title><author>Akioka, S. ; Feihui Li ; Malkowski, K. ; Raghavan, P. ; Kandemir, M. ; Irwin, M.J.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-8382ec81d4efccf6e9b7daff27614092b9df531595bd99f96c80c077a1d1d6c23</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2008</creationdate><topic>Costs</topic><topic>Delay</topic><topic>Energy consumption</topic><topic>Hardware</topic><topic>History</topic><topic>Manufacturing processes</topic><topic>Network-on-a-chip</topic><topic>System-on-a-chip</topic><topic>Topology</topic><topic>Wire</topic><toplevel>online_resources</toplevel><creatorcontrib>Akioka, S.</creatorcontrib><creatorcontrib>Feihui Li</creatorcontrib><creatorcontrib>Malkowski, K.</creatorcontrib><creatorcontrib>Raghavan, P.</creatorcontrib><creatorcontrib>Kandemir, M.</creatorcontrib><creatorcontrib>Irwin, M.J.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Akioka, S.</au><au>Feihui Li</au><au>Malkowski, K.</au><au>Raghavan, P.</au><au>Kandemir, M.</au><au>Irwin, M.J.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Ring data location prediction scheme for Non-Uniform Cache Architectures</atitle><btitle>2008 IEEE International Conference on Computer Design</btitle><stitle>ICCD</stitle><date>2008-10</date><risdate>2008</risdate><spage>693</spage><epage>698</epage><pages>693-698</pages><issn>1063-6404</issn><eissn>2576-6996</eissn><isbn>9781424426577</isbn><isbn>142442657X</isbn><eisbn>9781424426584</eisbn><eisbn>1424426588</eisbn><abstract>Increases in cache capacity are accompanied by growing wire delays due to technology scaling. Non-uniform cache architecture (NUCA) is one of proposed solutions to reducing the average access latency in such cache designs. While most of the prior NUCA work focuses on data placement, data replacement, and migration related issues, this paper studies the problem of data search (access) in NUCA. In our architecture we arrange sets of banks with equal access latency into rings. Our last access based (LAB) prediction scheme predicts the ring that is expected to contain the required data and checks the banks in that ring first for the data block sought. We compare our scheme to two alternate approaches: searching all rings in parallel, and searching rings sequentially. We show that our LAB ring prediction scheme reduces L2 energy significantly over the sequential and parallel schemes, while maintaining similar performance. Our LAB scheme reduces energy consumption by 15.9% relative to the sequential lookup scheme, and 53.8% relative to the parallel lookup scheme.</abstract><pub>IEEE</pub><doi>10.1109/ICCD.2008.4751936</doi><tpages>6</tpages></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | ISSN: 1063-6404 |
ispartof | 2008 IEEE International Conference on Computer Design, 2008, p.693-698 |
issn | 1063-6404 2576-6996 |
language | eng |
recordid | cdi_ieee_primary_4751936 |
source | IEEE Electronic Library (IEL) Conference Proceedings |
subjects | Costs Delay Energy consumption Hardware History Manufacturing processes Network-on-a-chip System-on-a-chip Topology Wire |
title | Ring data location prediction scheme for Non-Uniform Cache Architectures |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-14T00%3A16%3A22IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Ring%20data%20location%20prediction%20scheme%20for%20Non-Uniform%20Cache%20Architectures&rft.btitle=2008%20IEEE%20International%20Conference%20on%20Computer%20Design&rft.au=Akioka,%20S.&rft.date=2008-10&rft.spage=693&rft.epage=698&rft.pages=693-698&rft.issn=1063-6404&rft.eissn=2576-6996&rft.isbn=9781424426577&rft.isbn_list=142442657X&rft_id=info:doi/10.1109/ICCD.2008.4751936&rft_dat=%3Cieee_6IE%3E4751936%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=9781424426584&rft.eisbn_list=1424426588&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=4751936&rfr_iscdi=true |