Efficient Implementation of Floating-Point Reciprocator on FPGA

In this paper we have presented an efficient FPGA implementation of a reciprocator for both IEEE single-precision and double-precision floating point numbers. The method is based on the use of look-up tables and partial block multipliers. Compared with previously reported work, the modules occupy le...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Kumar Jaiswal, M., Chandrachoodan, N.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	binomial expansion Costs Delay double-precision Dynamic range Field programmable gate arrays Floating-point arithmetic FPGA Hardware partial block-multipliers reciprocator Signal processing algorithms Signal synthesis Table lookup Very large scale integration
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