Behavioral Synthesis of Asynchronous Circuits Using Syntax Directed Translation as Backend
The current state-of-the art in high-level synthesis of asynchronous circuits is syntax directed translation, which performs a one-to-one mapping of an HDL-description into a corresponding circuit. This paper presents a method for behavioral synthesis of asynchronous circuits which builds on top of...
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| Veröffentlicht in: | IEEE transactions on very large scale integration (VLSI) systems 2009-02, Vol.17 (2), p.248-261 |
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| container_title | IEEE transactions on very large scale integration (VLSI) systems |
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| creator | Nielsen, S.F. Sparso, J. Madsen, J. |
| description | The current state-of-the art in high-level synthesis of asynchronous circuits is syntax directed translation, which performs a one-to-one mapping of an HDL-description into a corresponding circuit. This paper presents a method for behavioral synthesis of asynchronous circuits which builds on top of syntax directed translation, and which allows the designer to perform automatic design space exploration guided by area or speed constraints. This paper presents an asynchronous implementation template consisting of a data-path and a control unit and its implementation using the asynchronous hardware description language Balsa. This ldquoconventionalrdquo template architecture allows us to adapt traditional synchronous synthesis techniques for resource sharing, scheduling, binding, etc., to the domain of asynchronous circuits. A prototype tool has been implemented on top of the Balsa framework, and the method is illustrated through the implementation of a set of example circuits. The main contributions of this paper are the fundamental idea, the template architecture and its implementation using asynchronous handshake components, and the implementation of a prototype tool. |
| doi_str_mv | 10.1109/TVLSI.2008.2005285 |
| format | Article |
| fullrecord | <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_ieee_primary_4749364</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>4749364</ieee_id><sourcerecordid>875017923</sourcerecordid><originalsourceid>FETCH-LOGICAL-c431t-62a3ecaca856f9a7c18f891afdde4fdf953667dd2079840961a1945d122b62c43</originalsourceid><addsrcrecordid>eNp9kT1PHDEQhlcokSAkfyBprEiBaom_vS7h-AjSSSk4UqSxJl47Z7J4wbOHuH8fH3eiSBEXtiU_88ozT9N8ZPSEMWq_Ln7Mb65POKXdZlO8U3vNAVPKtLauN_VOtWg7zuh-8w7xjlImpaUHzc-zsISnNBYYyM06T8uACckYySmus1-WMY8rJLNU_CpNSG4x5d8vIDyT81SCn0JPFgUyDjClMRNAcgb-T8j9--ZthAHDh9152NxeXixm39r596vr2em89VKwqdUcRPDgoVM6WjCedbGzDGLfBxn7aJXQ2vQ9p8Z2klrNgFmpesb5L81rxmFzvM19KOPjKuDk7hP6MAyQQ_2864yizFguKnn0X1JIpZjmtIKf_wHvxlXJtQtnGRdUK2sqxLeQLyNiCdE9lHQPZe0YdRsr7sWK21hxOyu16MsuGdDDEOvkfMLXyirICMk34Z-2XAohvD5LI63QUvwF86mVrA</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>912306597</pqid></control><display><type>article</type><title>Behavioral Synthesis of Asynchronous Circuits Using Syntax Directed Translation as Backend</title><source>IEEE Electronic Library (IEL)</source><creator>Nielsen, S.F. ; Sparso, J. ; Madsen, J.</creator><creatorcontrib>Nielsen, S.F. ; Sparso, J. ; Madsen, J.</creatorcontrib><description>The current state-of-the art in high-level synthesis of asynchronous circuits is syntax directed translation, which performs a one-to-one mapping of an HDL-description into a corresponding circuit. This paper presents a method for behavioral synthesis of asynchronous circuits which builds on top of syntax directed translation, and which allows the designer to perform automatic design space exploration guided by area or speed constraints. This paper presents an asynchronous implementation template consisting of a data-path and a control unit and its implementation using the asynchronous hardware description language Balsa. This ldquoconventionalrdquo template architecture allows us to adapt traditional synchronous synthesis techniques for resource sharing, scheduling, binding, etc., to the domain of asynchronous circuits. A prototype tool has been implemented on top of the Balsa framework, and the method is illustrated through the implementation of a set of example circuits. The main contributions of this paper are the fundamental idea, the template architecture and its implementation using asynchronous handshake components, and the implementation of a prototype tool.</description><identifier>ISSN: 1063-8210</identifier><identifier>EISSN: 1557-9999</identifier><identifier>DOI: 10.1109/TVLSI.2008.2005285</identifier><identifier>CODEN: IEVSE9</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; Architecture ; Asynchronous circuits ; Automatic control ; behavioral synthesis ; Circuit synthesis ; Circuits ; Electric, optical and optoelectronic circuits ; Electronics ; Exact sciences and technology ; Hardware design languages ; High level synthesis ; Job shop scheduling ; Prototypes ; Resource management ; Space exploration ; Studies ; Syntax ; Synthesis ; Theoretical study. Circuits analysis and design ; Translations ; Very large scale integration</subject><ispartof>IEEE transactions on very large scale integration (VLSI) systems, 2009-02, Vol.17 (2), p.248-261</ispartof><rights>2009 INIST-CNRS</rights><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2009</rights><lds50>peer_reviewed</lds50><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c431t-62a3ecaca856f9a7c18f891afdde4fdf953667dd2079840961a1945d122b62c43</citedby><cites>FETCH-LOGICAL-c431t-62a3ecaca856f9a7c18f891afdde4fdf953667dd2079840961a1945d122b62c43</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4749364$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27922,27923,54756</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4749364$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=21073427$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Nielsen, S.F.</creatorcontrib><creatorcontrib>Sparso, J.</creatorcontrib><creatorcontrib>Madsen, J.</creatorcontrib><title>Behavioral Synthesis of Asynchronous Circuits Using Syntax Directed Translation as Backend</title><title>IEEE transactions on very large scale integration (VLSI) systems</title><addtitle>TVLSI</addtitle><description>The current state-of-the art in high-level synthesis of asynchronous circuits is syntax directed translation, which performs a one-to-one mapping of an HDL-description into a corresponding circuit. This paper presents a method for behavioral synthesis of asynchronous circuits which builds on top of syntax directed translation, and which allows the designer to perform automatic design space exploration guided by area or speed constraints. This paper presents an asynchronous implementation template consisting of a data-path and a control unit and its implementation using the asynchronous hardware description language Balsa. This ldquoconventionalrdquo template architecture allows us to adapt traditional synchronous synthesis techniques for resource sharing, scheduling, binding, etc., to the domain of asynchronous circuits. A prototype tool has been implemented on top of the Balsa framework, and the method is illustrated through the implementation of a set of example circuits. The main contributions of this paper are the fundamental idea, the template architecture and its implementation using asynchronous handshake components, and the implementation of a prototype tool.</description><subject>Applied sciences</subject><subject>Architecture</subject><subject>Asynchronous circuits</subject><subject>Automatic control</subject><subject>behavioral synthesis</subject><subject>Circuit synthesis</subject><subject>Circuits</subject><subject>Electric, optical and optoelectronic circuits</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Hardware design languages</subject><subject>High level synthesis</subject><subject>Job shop scheduling</subject><subject>Prototypes</subject><subject>Resource management</subject><subject>Space exploration</subject><subject>Studies</subject><subject>Syntax</subject><subject>Synthesis</subject><subject>Theoretical study. Circuits analysis and design</subject><subject>Translations</subject><subject>Very large scale integration</subject><issn>1063-8210</issn><issn>1557-9999</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2009</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNp9kT1PHDEQhlcokSAkfyBprEiBaom_vS7h-AjSSSk4UqSxJl47Z7J4wbOHuH8fH3eiSBEXtiU_88ozT9N8ZPSEMWq_Ln7Mb65POKXdZlO8U3vNAVPKtLauN_VOtWg7zuh-8w7xjlImpaUHzc-zsISnNBYYyM06T8uACckYySmus1-WMY8rJLNU_CpNSG4x5d8vIDyT81SCn0JPFgUyDjClMRNAcgb-T8j9--ZthAHDh9152NxeXixm39r596vr2em89VKwqdUcRPDgoVM6WjCedbGzDGLfBxn7aJXQ2vQ9p8Z2klrNgFmpesb5L81rxmFzvM19KOPjKuDk7hP6MAyQQ_2864yizFguKnn0X1JIpZjmtIKf_wHvxlXJtQtnGRdUK2sqxLeQLyNiCdE9lHQPZe0YdRsr7sWK21hxOyu16MsuGdDDEOvkfMLXyirICMk34Z-2XAohvD5LI63QUvwF86mVrA</recordid><startdate>20090201</startdate><enddate>20090201</enddate><creator>Nielsen, S.F.</creator><creator>Sparso, J.</creator><creator>Madsen, J.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><scope>F28</scope><scope>FR3</scope></search><sort><creationdate>20090201</creationdate><title>Behavioral Synthesis of Asynchronous Circuits Using Syntax Directed Translation as Backend</title><author>Nielsen, S.F. ; Sparso, J. ; Madsen, J.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c431t-62a3ecaca856f9a7c18f891afdde4fdf953667dd2079840961a1945d122b62c43</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2009</creationdate><topic>Applied sciences</topic><topic>Architecture</topic><topic>Asynchronous circuits</topic><topic>Automatic control</topic><topic>behavioral synthesis</topic><topic>Circuit synthesis</topic><topic>Circuits</topic><topic>Electric, optical and optoelectronic circuits</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Hardware design languages</topic><topic>High level synthesis</topic><topic>Job shop scheduling</topic><topic>Prototypes</topic><topic>Resource management</topic><topic>Space exploration</topic><topic>Studies</topic><topic>Syntax</topic><topic>Synthesis</topic><topic>Theoretical study. Circuits analysis and design</topic><topic>Translations</topic><topic>Very large scale integration</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Nielsen, S.F.</creatorcontrib><creatorcontrib>Sparso, J.</creatorcontrib><creatorcontrib>Madsen, J.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Nielsen, S.F.</au><au>Sparso, J.</au><au>Madsen, J.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Behavioral Synthesis of Asynchronous Circuits Using Syntax Directed Translation as Backend</atitle><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle><stitle>TVLSI</stitle><date>2009-02-01</date><risdate>2009</risdate><volume>17</volume><issue>2</issue><spage>248</spage><epage>261</epage><pages>248-261</pages><issn>1063-8210</issn><eissn>1557-9999</eissn><coden>IEVSE9</coden><abstract>The current state-of-the art in high-level synthesis of asynchronous circuits is syntax directed translation, which performs a one-to-one mapping of an HDL-description into a corresponding circuit. This paper presents a method for behavioral synthesis of asynchronous circuits which builds on top of syntax directed translation, and which allows the designer to perform automatic design space exploration guided by area or speed constraints. This paper presents an asynchronous implementation template consisting of a data-path and a control unit and its implementation using the asynchronous hardware description language Balsa. This ldquoconventionalrdquo template architecture allows us to adapt traditional synchronous synthesis techniques for resource sharing, scheduling, binding, etc., to the domain of asynchronous circuits. A prototype tool has been implemented on top of the Balsa framework, and the method is illustrated through the implementation of a set of example circuits. The main contributions of this paper are the fundamental idea, the template architecture and its implementation using asynchronous handshake components, and the implementation of a prototype tool.</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/TVLSI.2008.2005285</doi><tpages>14</tpages><oa>free_for_read</oa></addata></record> |
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| identifier | ISSN: 1063-8210 |
| ispartof | IEEE transactions on very large scale integration (VLSI) systems, 2009-02, Vol.17 (2), p.248-261 |
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| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | Applied sciences Architecture Asynchronous circuits Automatic control behavioral synthesis Circuit synthesis Circuits Electric, optical and optoelectronic circuits Electronics Exact sciences and technology Hardware design languages High level synthesis Job shop scheduling Prototypes Resource management Space exploration Studies Syntax Synthesis Theoretical study. Circuits analysis and design Translations Very large scale integration |
| title | Behavioral Synthesis of Asynchronous Circuits Using Syntax Directed Translation as Backend |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-14T07%3A38%3A11IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Behavioral%20Synthesis%20of%20Asynchronous%20Circuits%20Using%20Syntax%20Directed%20Translation%20as%20Backend&rft.jtitle=IEEE%20transactions%20on%20very%20large%20scale%20integration%20(VLSI)%20systems&rft.au=Nielsen,%20S.F.&rft.date=2009-02-01&rft.volume=17&rft.issue=2&rft.spage=248&rft.epage=261&rft.pages=248-261&rft.issn=1063-8210&rft.eissn=1557-9999&rft.coden=IEVSE9&rft_id=info:doi/10.1109/TVLSI.2008.2005285&rft_dat=%3Cproquest_RIE%3E875017923%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=912306597&rft_id=info:pmid/&rft_ieee_id=4749364&rfr_iscdi=true |