A CDFG generating method from C program for LSI design

A CDFG generating method from C program for LSI design

This paper proposes a CDFG (control data flow graph) generating method from a C program for LSI design. At first, an application program described in C language is analyzed. And a hierarchical CDFG that maintains the program structure for optimal HW assignment is generated. After a generation of the...

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Hauptverfasser: Kato, T., Miyauchi, T., Osumi, Y., Yamauchi, H., Nishikado, H., Miyake, T., Kobayashi, S.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Cellular phones
Data engineering
Design engineering
Digital signal processing
Flow graphs
Hardware
High level synthesis
Large scale integration
Maintenance engineering
Research and development
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creator Kato, T.
Miyauchi, T.
Osumi, Y.
Yamauchi, H.
Nishikado, H.
Miyake, T.
Kobayashi, S.
description This paper proposes a CDFG (control data flow graph) generating method from a C program for LSI design. At first, an application program described in C language is analyzed. And a hierarchical CDFG that maintains the program structure for optimal HW assignment is generated. After a generation of the CDFG, every operation in the CDFG is partitioned to data operation or address operation for design of an architecture such as DSP, which has ALU and address operation unit separately.
doi_str_mv 10.1109/APCCAS.2008.4746177
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fullrecord <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_4746177</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>4746177</ieee_id><sourcerecordid>4746177</sourcerecordid><originalsourceid>FETCH-LOGICAL-i175t-f13356f33bb866437c1821d2ea9b347fe4d61be7240e2df03d3d2eafdbaba7b3</originalsourceid><addsrcrecordid>eNpVj1FLwzAUhSMyUGd_wV7yBzpzc2-T9rFENwcFhe19JCapFduOtC_-ex3uZeflcPgOBw5jKxBrAFE91e_G1Pu1FKJckyYFWt-wrNIlkCSSSFLeXmUoFuzhXK-ELAu8Y9k0fYk_UQFUiXumam6eN1vehiEkO3dDy_swf46exzT23PBTGttkex7HxJv9jvswde3wyBbRfk8hu_iSHTYvB_OaN2_bnambvANdzHkExEJFROdKpQj1B5QSvAy2ckg6BvIKXNCSRJA-CvR4htE766x2uGSr_9kuhHA8pa636ed4eY6_gOlIng</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>A CDFG generating method from C program for LSI design</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Kato, T. ; Miyauchi, T. ; Osumi, Y. ; Yamauchi, H. ; Nishikado, H. ; Miyake, T. ; Kobayashi, S.</creator><creatorcontrib>Kato, T. ; Miyauchi, T. ; Osumi, Y. ; Yamauchi, H. ; Nishikado, H. ; Miyake, T. ; Kobayashi, S.</creatorcontrib><description>This paper proposes a CDFG (control data flow graph) generating method from a C program for LSI design. At first, an application program described in C language is analyzed. And a hierarchical CDFG that maintains the program structure for optimal HW assignment is generated. After a generation of the CDFG, every operation in the CDFG is partitioned to data operation or address operation for design of an architecture such as DSP, which has ALU and address operation unit separately.</description><identifier>ISBN: 9781424423415</identifier><identifier>ISBN: 1424423414</identifier><identifier>EISBN: 9781424423422</identifier><identifier>EISBN: 1424423422</identifier><identifier>DOI: 10.1109/APCCAS.2008.4746177</identifier><identifier>LCCN: 2008902853</identifier><language>eng</language><publisher>IEEE</publisher><subject>Cellular phones ; Data engineering ; Design engineering ; Digital signal processing ; Flow graphs ; Hardware ; High level synthesis ; Large scale integration ; Maintenance engineering ; Research and development</subject><ispartof>APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems, 2008, p.936-939</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4746177$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,27902,54895</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4746177$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Kato, T.</creatorcontrib><creatorcontrib>Miyauchi, T.</creatorcontrib><creatorcontrib>Osumi, Y.</creatorcontrib><creatorcontrib>Yamauchi, H.</creatorcontrib><creatorcontrib>Nishikado, H.</creatorcontrib><creatorcontrib>Miyake, T.</creatorcontrib><creatorcontrib>Kobayashi, S.</creatorcontrib><title>A CDFG generating method from C program for LSI design</title><title>APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems</title><addtitle>APCCAS</addtitle><description>This paper proposes a CDFG (control data flow graph) generating method from a C program for LSI design. At first, an application program described in C language is analyzed. And a hierarchical CDFG that maintains the program structure for optimal HW assignment is generated. After a generation of the CDFG, every operation in the CDFG is partitioned to data operation or address operation for design of an architecture such as DSP, which has ALU and address operation unit separately.</description><subject>Cellular phones</subject><subject>Data engineering</subject><subject>Design engineering</subject><subject>Digital signal processing</subject><subject>Flow graphs</subject><subject>Hardware</subject><subject>High level synthesis</subject><subject>Large scale integration</subject><subject>Maintenance engineering</subject><subject>Research and development</subject><isbn>9781424423415</isbn><isbn>1424423414</isbn><isbn>9781424423422</isbn><isbn>1424423422</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2008</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpVj1FLwzAUhSMyUGd_wV7yBzpzc2-T9rFENwcFhe19JCapFduOtC_-ex3uZeflcPgOBw5jKxBrAFE91e_G1Pu1FKJckyYFWt-wrNIlkCSSSFLeXmUoFuzhXK-ELAu8Y9k0fYk_UQFUiXumam6eN1vehiEkO3dDy_swf46exzT23PBTGttkex7HxJv9jvswde3wyBbRfk8hu_iSHTYvB_OaN2_bnambvANdzHkExEJFROdKpQj1B5QSvAy2ckg6BvIKXNCSRJA-CvR4htE766x2uGSr_9kuhHA8pa636ed4eY6_gOlIng</recordid><startdate>200811</startdate><enddate>200811</enddate><creator>Kato, T.</creator><creator>Miyauchi, T.</creator><creator>Osumi, Y.</creator><creator>Yamauchi, H.</creator><creator>Nishikado, H.</creator><creator>Miyake, T.</creator><creator>Kobayashi, S.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200811</creationdate><title>A CDFG generating method from C program for LSI design</title><author>Kato, T. ; Miyauchi, T. ; Osumi, Y. ; Yamauchi, H. ; Nishikado, H. ; Miyake, T. ; Kobayashi, S.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-f13356f33bb866437c1821d2ea9b347fe4d61be7240e2df03d3d2eafdbaba7b3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2008</creationdate><topic>Cellular phones</topic><topic>Data engineering</topic><topic>Design engineering</topic><topic>Digital signal processing</topic><topic>Flow graphs</topic><topic>Hardware</topic><topic>High level synthesis</topic><topic>Large scale integration</topic><topic>Maintenance engineering</topic><topic>Research and development</topic><toplevel>online_resources</toplevel><creatorcontrib>Kato, T.</creatorcontrib><creatorcontrib>Miyauchi, T.</creatorcontrib><creatorcontrib>Osumi, Y.</creatorcontrib><creatorcontrib>Yamauchi, H.</creatorcontrib><creatorcontrib>Nishikado, H.</creatorcontrib><creatorcontrib>Miyake, T.</creatorcontrib><creatorcontrib>Kobayashi, S.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Kato, T.</au><au>Miyauchi, T.</au><au>Osumi, Y.</au><au>Yamauchi, H.</au><au>Nishikado, H.</au><au>Miyake, T.</au><au>Kobayashi, S.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A CDFG generating method from C program for LSI design</atitle><btitle>APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems</btitle><stitle>APCCAS</stitle><date>2008-11</date><risdate>2008</risdate><spage>936</spage><epage>939</epage><pages>936-939</pages><isbn>9781424423415</isbn><isbn>1424423414</isbn><eisbn>9781424423422</eisbn><eisbn>1424423422</eisbn><abstract>This paper proposes a CDFG (control data flow graph) generating method from a C program for LSI design. At first, an application program described in C language is analyzed. And a hierarchical CDFG that maintains the program structure for optimal HW assignment is generated. After a generation of the CDFG, every operation in the CDFG is partitioned to data operation or address operation for design of an architecture such as DSP, which has ALU and address operation unit separately.</abstract><pub>IEEE</pub><doi>10.1109/APCCAS.2008.4746177</doi><tpages>4</tpages></addata></record>
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subjects Cellular phones
Data engineering
Design engineering
Digital signal processing
Flow graphs
Hardware
High level synthesis
Large scale integration
Maintenance engineering
Research and development
title A CDFG generating method from C program for LSI design
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-12T11%3A26%3A33IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=A%20CDFG%20generating%20method%20from%20C%20program%20for%20LSI%20design&rft.btitle=APCCAS%202008%20-%202008%20IEEE%20Asia%20Pacific%20Conference%20on%20Circuits%20and%20Systems&rft.au=Kato,%20T.&rft.date=2008-11&rft.spage=936&rft.epage=939&rft.pages=936-939&rft.isbn=9781424423415&rft.isbn_list=1424423414&rft_id=info:doi/10.1109/APCCAS.2008.4746177&rft_dat=%3Cieee_6IE%3E4746177%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=9781424423422&rft.eisbn_list=1424423422&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=4746177&rfr_iscdi=true