A new wideband, high-linear passive Sample and Hold structure suitable for high-speed, high-resolution ADCs
In this paper a new passive sample and hold (S/H) structure employing a modified sampling switch circuit has been presented. In order to reach wideband input with high linear sampling, the sampling switch voltage dependency on input signal is reduced, dramatically. Furthermore, the proposed structur...
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Tagungsbericht |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 152 |
|---|---|
| container_issue | |
| container_start_page | 149 |
| container_title | |
| container_volume | |
| creator | Sadeghipour, K.D. |
| description | In this paper a new passive sample and hold (S/H) structure employing a modified sampling switch circuit has been presented. In order to reach wideband input with high linear sampling, the sampling switch voltage dependency on input signal is reduced, dramatically. Furthermore, the proposed structure reduces signal feedthrough for high frequency inputs as well as enabling the merge of offset cancellation cycle for S/H subsequent stage with the sampling cycle, simultaneously. The simulation results for the designed 12-bit, 250 Msps S/H in standard 0.35 mum CMOS process with 500 MHz input bandwidth, show 14 dB and 10 dB improvement on THD and signal feedthrough, respectively. |
| doi_str_mv | 10.1109/APCCAS.2008.4745982 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_4745982</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>4745982</ieee_id><sourcerecordid>4745982</sourcerecordid><originalsourceid>FETCH-LOGICAL-i175t-2e65b00ff925b2939312f12a5997b172de23cc26eeed66757147e979d1c30e333</originalsourceid><addsrcrecordid>eNpVkM1OwzAQhI1QJaD0CXrxA5Bgr-04Pkbhp0iVQCqcKyfZUEOaRHZCxdsT1HJgL6PVfDsrDSFLzmLOmbnNXvI828TAWBpLLZVJ4YwsjE65BClBSIDzfztXM3L1ixsGqRIXZBHCB5tGKi4NuySfGW3xQA-uwsK21Q3dufdd1LgWrae9DcF9Id3Yfd8gnXy66pqKhsGP5TB6pGF0gy0mr-788TT0iH8xHkPXjIPrWprd5eGazGrbBFycdE7eHu5f81W0fn58yrN15LhWQwSYqIKxujagCjDCCA41B6uM0QXXUCGIsoQEp0dJopXmUqPRpuKlYCiEmJPlMddNyLb3bm_99_bUl_gBE5Jb6A</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>A new wideband, high-linear passive Sample and Hold structure suitable for high-speed, high-resolution ADCs</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Sadeghipour, K.D.</creator><creatorcontrib>Sadeghipour, K.D.</creatorcontrib><description>In this paper a new passive sample and hold (S/H) structure employing a modified sampling switch circuit has been presented. In order to reach wideband input with high linear sampling, the sampling switch voltage dependency on input signal is reduced, dramatically. Furthermore, the proposed structure reduces signal feedthrough for high frequency inputs as well as enabling the merge of offset cancellation cycle for S/H subsequent stage with the sampling cycle, simultaneously. The simulation results for the designed 12-bit, 250 Msps S/H in standard 0.35 mum CMOS process with 500 MHz input bandwidth, show 14 dB and 10 dB improvement on THD and signal feedthrough, respectively.</description><identifier>ISBN: 9781424423415</identifier><identifier>ISBN: 1424423414</identifier><identifier>EISBN: 9781424423422</identifier><identifier>EISBN: 1424423422</identifier><identifier>DOI: 10.1109/APCCAS.2008.4745982</identifier><identifier>LCCN: 2008902853</identifier><language>eng</language><publisher>IEEE</publisher><subject>Bandwidth ; CMOS process ; Frequency ; Sampling methods ; Signal design ; Signal sampling ; Switches ; Switching circuits ; Voltage ; Wideband</subject><ispartof>APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems, 2008, p.149-152</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4745982$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,27902,54895</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4745982$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Sadeghipour, K.D.</creatorcontrib><title>A new wideband, high-linear passive Sample and Hold structure suitable for high-speed, high-resolution ADCs</title><title>APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems</title><addtitle>APCCAS</addtitle><description>In this paper a new passive sample and hold (S/H) structure employing a modified sampling switch circuit has been presented. In order to reach wideband input with high linear sampling, the sampling switch voltage dependency on input signal is reduced, dramatically. Furthermore, the proposed structure reduces signal feedthrough for high frequency inputs as well as enabling the merge of offset cancellation cycle for S/H subsequent stage with the sampling cycle, simultaneously. The simulation results for the designed 12-bit, 250 Msps S/H in standard 0.35 mum CMOS process with 500 MHz input bandwidth, show 14 dB and 10 dB improvement on THD and signal feedthrough, respectively.</description><subject>Bandwidth</subject><subject>CMOS process</subject><subject>Frequency</subject><subject>Sampling methods</subject><subject>Signal design</subject><subject>Signal sampling</subject><subject>Switches</subject><subject>Switching circuits</subject><subject>Voltage</subject><subject>Wideband</subject><isbn>9781424423415</isbn><isbn>1424423414</isbn><isbn>9781424423422</isbn><isbn>1424423422</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2008</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpVkM1OwzAQhI1QJaD0CXrxA5Bgr-04Pkbhp0iVQCqcKyfZUEOaRHZCxdsT1HJgL6PVfDsrDSFLzmLOmbnNXvI828TAWBpLLZVJ4YwsjE65BClBSIDzfztXM3L1ixsGqRIXZBHCB5tGKi4NuySfGW3xQA-uwsK21Q3dufdd1LgWrae9DcF9Id3Yfd8gnXy66pqKhsGP5TB6pGF0gy0mr-788TT0iH8xHkPXjIPrWprd5eGazGrbBFycdE7eHu5f81W0fn58yrN15LhWQwSYqIKxujagCjDCCA41B6uM0QXXUCGIsoQEp0dJopXmUqPRpuKlYCiEmJPlMddNyLb3bm_99_bUl_gBE5Jb6A</recordid><startdate>200811</startdate><enddate>200811</enddate><creator>Sadeghipour, K.D.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200811</creationdate><title>A new wideband, high-linear passive Sample and Hold structure suitable for high-speed, high-resolution ADCs</title><author>Sadeghipour, K.D.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-2e65b00ff925b2939312f12a5997b172de23cc26eeed66757147e979d1c30e333</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2008</creationdate><topic>Bandwidth</topic><topic>CMOS process</topic><topic>Frequency</topic><topic>Sampling methods</topic><topic>Signal design</topic><topic>Signal sampling</topic><topic>Switches</topic><topic>Switching circuits</topic><topic>Voltage</topic><topic>Wideband</topic><toplevel>online_resources</toplevel><creatorcontrib>Sadeghipour, K.D.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Sadeghipour, K.D.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A new wideband, high-linear passive Sample and Hold structure suitable for high-speed, high-resolution ADCs</atitle><btitle>APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems</btitle><stitle>APCCAS</stitle><date>2008-11</date><risdate>2008</risdate><spage>149</spage><epage>152</epage><pages>149-152</pages><isbn>9781424423415</isbn><isbn>1424423414</isbn><eisbn>9781424423422</eisbn><eisbn>1424423422</eisbn><abstract>In this paper a new passive sample and hold (S/H) structure employing a modified sampling switch circuit has been presented. In order to reach wideband input with high linear sampling, the sampling switch voltage dependency on input signal is reduced, dramatically. Furthermore, the proposed structure reduces signal feedthrough for high frequency inputs as well as enabling the merge of offset cancellation cycle for S/H subsequent stage with the sampling cycle, simultaneously. The simulation results for the designed 12-bit, 250 Msps S/H in standard 0.35 mum CMOS process with 500 MHz input bandwidth, show 14 dB and 10 dB improvement on THD and signal feedthrough, respectively.</abstract><pub>IEEE</pub><doi>10.1109/APCCAS.2008.4745982</doi><tpages>4</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISBN: 9781424423415 |
| ispartof | APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems, 2008, p.149-152 |
| issn | |
| language | eng |
| recordid | cdi_ieee_primary_4745982 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Bandwidth CMOS process Frequency Sampling methods Signal design Signal sampling Switches Switching circuits Voltage Wideband |
| title | A new wideband, high-linear passive Sample and Hold structure suitable for high-speed, high-resolution ADCs |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-12T14%3A10%3A01IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=A%20new%20wideband,%20high-linear%20passive%20Sample%20and%20Hold%20structure%20suitable%20for%20high-speed,%20high-resolution%20ADCs&rft.btitle=APCCAS%202008%20-%202008%20IEEE%20Asia%20Pacific%20Conference%20on%20Circuits%20and%20Systems&rft.au=Sadeghipour,%20K.D.&rft.date=2008-11&rft.spage=149&rft.epage=152&rft.pages=149-152&rft.isbn=9781424423415&rft.isbn_list=1424423414&rft_id=info:doi/10.1109/APCCAS.2008.4745982&rft_dat=%3Cieee_6IE%3E4745982%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=9781424423422&rft.eisbn_list=1424423422&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=4745982&rfr_iscdi=true |