A 10MHz to 600MHz low jitter CMOS PLL for clock multiplication

This paper describes a phase-locked loop (PLL) designed for clock multiplication. The PLL has a locking range from 10 MHz to 600 MHz at 1.8 V power supply. It has a very low peak-to-peak jitter which less than 50 ps at 150 MHz output frequency. It has been fabricated in a 0.18 ¿m CMOS process. The a...

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Bibliographische Detailangaben

Hauptverfasser:	Bing Fan, Luo-sheng Li, Zi-qiao Chu, Dong-hui Wang, Chao-huan Hou
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Charge pumps Circuits clock jitter Clocks Energy consumption Filters Jitter Phase detection Phase frequency detector Phase locked loops PLL VCO Voltage-controlled oscillators
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