Thermal noise performance in recent CMOS technologies
This paper reviews the measurement and modeling issues of the channel thermal noise in MOSFETs as a result of the aggressive reduction of the channel length into the sub-100 nm regimes. It also shows the noise performance of devices in 65 nm CMOS technology.
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| creator | Chih-Hung Chen Bigchoug Hung Sheng-Yi Huang Jin-Shyong Jan Liang, V. Chune-Sin Yeh |
| description | This paper reviews the measurement and modeling issues of the channel thermal noise in MOSFETs as a result of the aggressive reduction of the channel length into the sub-100 nm regimes. It also shows the noise performance of devices in 65 nm CMOS technology. |
| doi_str_mv | 10.1109/ICSICT.2008.4734584 |
| format | Conference Proceeding |
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| identifier | ISBN: 9781424421855 |
| ispartof | 2008 9th International Conference on Solid-State and Integrated-Circuit Technology, 2008, p.476-479 |
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| language | eng |
| recordid | cdi_ieee_primary_4734584 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Analog integrated circuits Application specific integrated circuits CMOS technology Equations High speed integrated circuits Integrated circuit noise Microelectronics MOSFETs Noise measurement Radio frequency |
| title | Thermal noise performance in recent CMOS technologies |
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