A single-loop DLL using an OR-AND duty-cycle correction technique

In this paper, we report a single-loop delay-locked loop (DLL) using a novel OR-AND duty-cycle correction (DCC) circuit. The proposed OR-AND DCC circuit employs both an analog blocks to detect duty error precisely and a digital block to control duty-error easily. To prove the proposed concepts, a si...

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
Hauptverfasser:	Keun-Soo Song, Cheul-Hee Koo, Nak-Kyu Park, Kwan-Weon Kim, Young-Jung Choi, Jin-Hong Ahn, Byong-Tae Chung
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Circuit simulation Clocks CMOS process Delay Digital control Error correction Frequency Jitter Power supplies SPICE
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

container_end_page	248
container_issue
container_start_page	245
container_title
container_volume
creator	Keun-Soo Song Cheul-Hee Koo Nak-Kyu Park Kwan-Weon Kim Young-Jung Choi Jin-Hong Ahn Byong-Tae Chung
description	In this paper, we report a single-loop delay-locked loop (DLL) using a novel OR-AND duty-cycle correction (DCC) circuit. The proposed OR-AND DCC circuit employs both an analog blocks to detect duty error precisely and a digital block to control duty-error easily. To prove the proposed concepts, a single-loop DLL employing the proposed OR-AND DCC is demonstrated with SPICE simulation. The DLL using 0.1-mum CMOS process provides clocks with 16-psec peak-to-peak jitter at 1-GHz operating frequency and spends 20-mA bias current at 1.8-V power supply. The proposed DCC has the accuracy of plusmn1 % for plusmn25 % duty error and 300 cycles duty-correction time in the range of 100 MHz -1.3 GHz operating frequencies.
doi_str_mv	10.1109/ASSCC.2008.4708774
format	Conference Proceeding
fullrecord	<record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_4708774</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>4708774</ieee_id><sourcerecordid>4708774</sourcerecordid><originalsourceid>FETCH-LOGICAL-i175t-666170b10bbf44f7d45b1c5a5b56b40af7186fb292dc268f2ceaff82da9d7ebb3</originalsourceid><addsrcrecordid>eNpVkEtOwzAYhI1QJaDkArDxBRxs5_cjyyiFghS1UgvrynZsMApJyWOR20NFN8xmNJ9GsxiE7hhNGaP5Q7Hfl2XKKdUpKKqVgguU5Eoz4ABcUqEv_2VgC3RzqucUtJRXKBmGT_orEJnk8hoVBR5i-9540nTdEa-qCk8ngE2LtztSbFa4nsaZuNk1Hruu770bY9fi0buPNn5P_hYtgmkGn5x9id6eHl_LZ1Jt1y9lUZHIlBiJlJIpahm1NgAEVYOwzAkjrJAWqAmKaRksz3ntuNSBO29C0Lw2ea28tdkS3f_tRu_94djHL9PPh_ML2Q-aQ01a</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>A single-loop DLL using an OR-AND duty-cycle correction technique</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Keun-Soo Song ; Cheul-Hee Koo ; Nak-Kyu Park ; Kwan-Weon Kim ; Young-Jung Choi ; Jin-Hong Ahn ; Byong-Tae Chung</creator><creatorcontrib>Keun-Soo Song ; Cheul-Hee Koo ; Nak-Kyu Park ; Kwan-Weon Kim ; Young-Jung Choi ; Jin-Hong Ahn ; Byong-Tae Chung</creatorcontrib><description>In this paper, we report a single-loop delay-locked loop (DLL) using a novel OR-AND duty-cycle correction (DCC) circuit. The proposed OR-AND DCC circuit employs both an analog blocks to detect duty error precisely and a digital block to control duty-error easily. To prove the proposed concepts, a single-loop DLL employing the proposed OR-AND DCC is demonstrated with SPICE simulation. The DLL using 0.1-mum CMOS process provides clocks with 16-psec peak-to-peak jitter at 1-GHz operating frequency and spends 20-mA bias current at 1.8-V power supply. The proposed DCC has the accuracy of plusmn1 % for plusmn25 % duty error and 300 cycles duty-correction time in the range of 100 MHz -1.3 GHz operating frequencies.</description><identifier>ISBN: 9781424426041</identifier><identifier>ISBN: 1424426049</identifier><identifier>EISBN: 9781424426058</identifier><identifier>EISBN: 1424426057</identifier><identifier>DOI: 10.1109/ASSCC.2008.4708774</identifier><identifier>LCCN: 2008904866</identifier><language>eng</language><publisher>IEEE</publisher><subject>Circuit simulation ; Clocks ; CMOS process ; Delay ; Digital control ; Error correction ; Frequency ; Jitter ; Power supplies ; SPICE</subject><ispartof>2008 IEEE Asian Solid-State Circuits Conference, 2008, p.245-248</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4708774$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4708774$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Keun-Soo Song</creatorcontrib><creatorcontrib>Cheul-Hee Koo</creatorcontrib><creatorcontrib>Nak-Kyu Park</creatorcontrib><creatorcontrib>Kwan-Weon Kim</creatorcontrib><creatorcontrib>Young-Jung Choi</creatorcontrib><creatorcontrib>Jin-Hong Ahn</creatorcontrib><creatorcontrib>Byong-Tae Chung</creatorcontrib><title>A single-loop DLL using an OR-AND duty-cycle correction technique</title><title>2008 IEEE Asian Solid-State Circuits Conference</title><addtitle>ASSCC</addtitle><description>In this paper, we report a single-loop delay-locked loop (DLL) using a novel OR-AND duty-cycle correction (DCC) circuit. The proposed OR-AND DCC circuit employs both an analog blocks to detect duty error precisely and a digital block to control duty-error easily. To prove the proposed concepts, a single-loop DLL employing the proposed OR-AND DCC is demonstrated with SPICE simulation. The DLL using 0.1-mum CMOS process provides clocks with 16-psec peak-to-peak jitter at 1-GHz operating frequency and spends 20-mA bias current at 1.8-V power supply. The proposed DCC has the accuracy of plusmn1 % for plusmn25 % duty error and 300 cycles duty-correction time in the range of 100 MHz -1.3 GHz operating frequencies.</description><subject>Circuit simulation</subject><subject>Clocks</subject><subject>CMOS process</subject><subject>Delay</subject><subject>Digital control</subject><subject>Error correction</subject><subject>Frequency</subject><subject>Jitter</subject><subject>Power supplies</subject><subject>SPICE</subject><isbn>9781424426041</isbn><isbn>1424426049</isbn><isbn>9781424426058</isbn><isbn>1424426057</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2008</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpVkEtOwzAYhI1QJaDkArDxBRxs5_cjyyiFghS1UgvrynZsMApJyWOR20NFN8xmNJ9GsxiE7hhNGaP5Q7Hfl2XKKdUpKKqVgguU5Eoz4ABcUqEv_2VgC3RzqucUtJRXKBmGT_orEJnk8hoVBR5i-9540nTdEa-qCk8ngE2LtztSbFa4nsaZuNk1Hruu770bY9fi0buPNn5P_hYtgmkGn5x9id6eHl_LZ1Jt1y9lUZHIlBiJlJIpahm1NgAEVYOwzAkjrJAWqAmKaRksz3ntuNSBO29C0Lw2ea28tdkS3f_tRu_94djHL9PPh_ML2Q-aQ01a</recordid><startdate>200811</startdate><enddate>200811</enddate><creator>Keun-Soo Song</creator><creator>Cheul-Hee Koo</creator><creator>Nak-Kyu Park</creator><creator>Kwan-Weon Kim</creator><creator>Young-Jung Choi</creator><creator>Jin-Hong Ahn</creator><creator>Byong-Tae Chung</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200811</creationdate><title>A single-loop DLL using an OR-AND duty-cycle correction technique</title><author>Keun-Soo Song ; Cheul-Hee Koo ; Nak-Kyu Park ; Kwan-Weon Kim ; Young-Jung Choi ; Jin-Hong Ahn ; Byong-Tae Chung</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-666170b10bbf44f7d45b1c5a5b56b40af7186fb292dc268f2ceaff82da9d7ebb3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2008</creationdate><topic>Circuit simulation</topic><topic>Clocks</topic><topic>CMOS process</topic><topic>Delay</topic><topic>Digital control</topic><topic>Error correction</topic><topic>Frequency</topic><topic>Jitter</topic><topic>Power supplies</topic><topic>SPICE</topic><toplevel>online_resources</toplevel><creatorcontrib>Keun-Soo Song</creatorcontrib><creatorcontrib>Cheul-Hee Koo</creatorcontrib><creatorcontrib>Nak-Kyu Park</creatorcontrib><creatorcontrib>Kwan-Weon Kim</creatorcontrib><creatorcontrib>Young-Jung Choi</creatorcontrib><creatorcontrib>Jin-Hong Ahn</creatorcontrib><creatorcontrib>Byong-Tae Chung</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Keun-Soo Song</au><au>Cheul-Hee Koo</au><au>Nak-Kyu Park</au><au>Kwan-Weon Kim</au><au>Young-Jung Choi</au><au>Jin-Hong Ahn</au><au>Byong-Tae Chung</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A single-loop DLL using an OR-AND duty-cycle correction technique</atitle><btitle>2008 IEEE Asian Solid-State Circuits Conference</btitle><stitle>ASSCC</stitle><date>2008-11</date><risdate>2008</risdate><spage>245</spage><epage>248</epage><pages>245-248</pages><isbn>9781424426041</isbn><isbn>1424426049</isbn><eisbn>9781424426058</eisbn><eisbn>1424426057</eisbn><abstract>In this paper, we report a single-loop delay-locked loop (DLL) using a novel OR-AND duty-cycle correction (DCC) circuit. The proposed OR-AND DCC circuit employs both an analog blocks to detect duty error precisely and a digital block to control duty-error easily. To prove the proposed concepts, a single-loop DLL employing the proposed OR-AND DCC is demonstrated with SPICE simulation. The DLL using 0.1-mum CMOS process provides clocks with 16-psec peak-to-peak jitter at 1-GHz operating frequency and spends 20-mA bias current at 1.8-V power supply. The proposed DCC has the accuracy of plusmn1 % for plusmn25 % duty error and 300 cycles duty-correction time in the range of 100 MHz -1.3 GHz operating frequencies.</abstract><pub>IEEE</pub><doi>10.1109/ASSCC.2008.4708774</doi><tpages>4</tpages></addata></record>
fulltext	fulltext_linktorsrc
identifier	ISBN: 9781424426041
ispartof	2008 IEEE Asian Solid-State Circuits Conference, 2008, p.245-248
issn
language	eng
recordid	cdi_ieee_primary_4708774
source	IEEE Electronic Library (IEL) Conference Proceedings
subjects	Circuit simulation Clocks CMOS process Delay Digital control Error correction Frequency Jitter Power supplies SPICE
title	A single-loop DLL using an OR-AND duty-cycle correction technique
url	https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-06T00%3A16%3A27IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=A%20single-loop%20DLL%20using%20an%20OR-AND%20duty-cycle%20correction%20technique&rft.btitle=2008%20IEEE%20Asian%20Solid-State%20Circuits%20Conference&rft.au=Keun-Soo%20Song&rft.date=2008-11&rft.spage=245&rft.epage=248&rft.pages=245-248&rft.isbn=9781424426041&rft.isbn_list=1424426049&rft_id=info:doi/10.1109/ASSCC.2008.4708774&rft_dat=%3Cieee_6IE%3E4708774%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=9781424426058&rft.eisbn_list=1424426057&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=4708774&rfr_iscdi=true