Functional Test and Speed/Power Sorting of the IBM POWER6 and Z10 Processors
The 5 GHz IBM POWER6 processor (P6) and newest Z10 4.4 GHz processor utilized a custom combination of structural and functional testing delivering improved test costs and accelerated SPQL learning over previous IBM processor generations.
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creator | Pham, T.N. Clougherty, F. Salem, G. Crafts, J.M. Tetzloff, J. Moczygemba, P. Skergan, T.M. |
description | The 5 GHz IBM POWER6 processor (P6) and newest Z10 4.4 GHz processor utilized a custom combination of structural and functional testing delivering improved test costs and accelerated SPQL learning over previous IBM processor generations. |
doi_str_mv | 10.1109/TEST.2008.4700598 |
format | Conference Proceeding |
fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_4700598</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>4700598</ieee_id><sourcerecordid>4700598</sourcerecordid><originalsourceid>FETCH-LOGICAL-i90t-d27e32ba132bc538c982209b5a514f5e1853a9ef22b5ab381eaa322aecac84f83</originalsourceid><addsrcrecordid>eNo1UNtKw0AUXG9gWvsB4sv-QNqzZ7Nm91FLqoVIgwkIvpTN5kQjNSnZFPHvDVphmIGZYR6GsWsBcyHALIokL-YIoOdRDKCMPmETEWE0AqQ-ZQHKWIeICs7YzMT6P0N5zgIB2oRSSXPJJt5_ACAohIClq0PrhqZr7Y4X5Adu24rne6JqkXVf1PO864emfeNdzYd34uv7J55tXpLn29_mqwCe9Z0j77veX7GL2u48zY46ZcUqKZaPYbp5WC_v0rAxMIQVxiSxtGIkp6R2RiOCKZVVIqoVCa2kNVQjjlYptSBrJaIlZ52Oai2n7OZvtiGi7b5vPm3_vT2eIn8A9v5PrA</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Functional Test and Speed/Power Sorting of the IBM POWER6 and Z10 Processors</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Pham, T.N. ; Clougherty, F. ; Salem, G. ; Crafts, J.M. ; Tetzloff, J. ; Moczygemba, P. ; Skergan, T.M.</creator><creatorcontrib>Pham, T.N. ; Clougherty, F. ; Salem, G. ; Crafts, J.M. ; Tetzloff, J. ; Moczygemba, P. ; Skergan, T.M.</creatorcontrib><description>The 5 GHz IBM POWER6 processor (P6) and newest Z10 4.4 GHz processor utilized a custom combination of structural and functional testing delivering improved test costs and accelerated SPQL learning over previous IBM processor generations.</description><identifier>ISSN: 1089-3539</identifier><identifier>ISBN: 9781424424023</identifier><identifier>ISBN: 142442402X</identifier><identifier>EISSN: 2378-2250</identifier><identifier>EISBN: 1424424038</identifier><identifier>EISBN: 9781424424030</identifier><identifier>DOI: 10.1109/TEST.2008.4700598</identifier><language>eng</language><publisher>IEEE</publisher><subject>Circuit faults ; Circuit testing ; Communication system control ; Cost function ; Logic arrays ; Logic programming ; Logic testing ; Sorting ; System testing ; System-on-a-chip</subject><ispartof>2008 IEEE International Test Conference, 2008, p.1-7</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4700598$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4700598$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Pham, T.N.</creatorcontrib><creatorcontrib>Clougherty, F.</creatorcontrib><creatorcontrib>Salem, G.</creatorcontrib><creatorcontrib>Crafts, J.M.</creatorcontrib><creatorcontrib>Tetzloff, J.</creatorcontrib><creatorcontrib>Moczygemba, P.</creatorcontrib><creatorcontrib>Skergan, T.M.</creatorcontrib><title>Functional Test and Speed/Power Sorting of the IBM POWER6 and Z10 Processors</title><title>2008 IEEE International Test Conference</title><addtitle>TEST</addtitle><description>The 5 GHz IBM POWER6 processor (P6) and newest Z10 4.4 GHz processor utilized a custom combination of structural and functional testing delivering improved test costs and accelerated SPQL learning over previous IBM processor generations.</description><subject>Circuit faults</subject><subject>Circuit testing</subject><subject>Communication system control</subject><subject>Cost function</subject><subject>Logic arrays</subject><subject>Logic programming</subject><subject>Logic testing</subject><subject>Sorting</subject><subject>System testing</subject><subject>System-on-a-chip</subject><issn>1089-3539</issn><issn>2378-2250</issn><isbn>9781424424023</isbn><isbn>142442402X</isbn><isbn>1424424038</isbn><isbn>9781424424030</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2008</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNo1UNtKw0AUXG9gWvsB4sv-QNqzZ7Nm91FLqoVIgwkIvpTN5kQjNSnZFPHvDVphmIGZYR6GsWsBcyHALIokL-YIoOdRDKCMPmETEWE0AqQ-ZQHKWIeICs7YzMT6P0N5zgIB2oRSSXPJJt5_ACAohIClq0PrhqZr7Y4X5Adu24rne6JqkXVf1PO864emfeNdzYd34uv7J55tXpLn29_mqwCe9Z0j77veX7GL2u48zY46ZcUqKZaPYbp5WC_v0rAxMIQVxiSxtGIkp6R2RiOCKZVVIqoVCa2kNVQjjlYptSBrJaIlZ52Oai2n7OZvtiGi7b5vPm3_vT2eIn8A9v5PrA</recordid><startdate>200810</startdate><enddate>200810</enddate><creator>Pham, T.N.</creator><creator>Clougherty, F.</creator><creator>Salem, G.</creator><creator>Crafts, J.M.</creator><creator>Tetzloff, J.</creator><creator>Moczygemba, P.</creator><creator>Skergan, T.M.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>200810</creationdate><title>Functional Test and Speed/Power Sorting of the IBM POWER6 and Z10 Processors</title><author>Pham, T.N. ; Clougherty, F. ; Salem, G. ; Crafts, J.M. ; Tetzloff, J. ; Moczygemba, P. ; Skergan, T.M.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-d27e32ba132bc538c982209b5a514f5e1853a9ef22b5ab381eaa322aecac84f83</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2008</creationdate><topic>Circuit faults</topic><topic>Circuit testing</topic><topic>Communication system control</topic><topic>Cost function</topic><topic>Logic arrays</topic><topic>Logic programming</topic><topic>Logic testing</topic><topic>Sorting</topic><topic>System testing</topic><topic>System-on-a-chip</topic><toplevel>online_resources</toplevel><creatorcontrib>Pham, T.N.</creatorcontrib><creatorcontrib>Clougherty, F.</creatorcontrib><creatorcontrib>Salem, G.</creatorcontrib><creatorcontrib>Crafts, J.M.</creatorcontrib><creatorcontrib>Tetzloff, J.</creatorcontrib><creatorcontrib>Moczygemba, P.</creatorcontrib><creatorcontrib>Skergan, T.M.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Pham, T.N.</au><au>Clougherty, F.</au><au>Salem, G.</au><au>Crafts, J.M.</au><au>Tetzloff, J.</au><au>Moczygemba, P.</au><au>Skergan, T.M.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Functional Test and Speed/Power Sorting of the IBM POWER6 and Z10 Processors</atitle><btitle>2008 IEEE International Test Conference</btitle><stitle>TEST</stitle><date>2008-10</date><risdate>2008</risdate><spage>1</spage><epage>7</epage><pages>1-7</pages><issn>1089-3539</issn><eissn>2378-2250</eissn><isbn>9781424424023</isbn><isbn>142442402X</isbn><eisbn>1424424038</eisbn><eisbn>9781424424030</eisbn><abstract>The 5 GHz IBM POWER6 processor (P6) and newest Z10 4.4 GHz processor utilized a custom combination of structural and functional testing delivering improved test costs and accelerated SPQL learning over previous IBM processor generations.</abstract><pub>IEEE</pub><doi>10.1109/TEST.2008.4700598</doi><tpages>7</tpages></addata></record> |
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source | IEEE Electronic Library (IEL) Conference Proceedings |
subjects | Circuit faults Circuit testing Communication system control Cost function Logic arrays Logic programming Logic testing Sorting System testing System-on-a-chip |
title | Functional Test and Speed/Power Sorting of the IBM POWER6 and Z10 Processors |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-29T18%3A52%3A50IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Functional%20Test%20and%20Speed/Power%20Sorting%20of%20the%20IBM%20POWER6%20and%20Z10%20Processors&rft.btitle=2008%20IEEE%20International%20Test%20Conference&rft.au=Pham,%20T.N.&rft.date=2008-10&rft.spage=1&rft.epage=7&rft.pages=1-7&rft.issn=1089-3539&rft.eissn=2378-2250&rft.isbn=9781424424023&rft.isbn_list=142442402X&rft_id=info:doi/10.1109/TEST.2008.4700598&rft_dat=%3Cieee_6IE%3E4700598%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=1424424038&rft.eisbn_list=9781424424030&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=4700598&rfr_iscdi=true |