MARTE based modeling approach for Partial Dynamic Reconfigurable FPGAs

As System-on-Chip (SoC) architectures become pivotal for designing embedded systems, the SoC design complexity continues to increase exponentially necessitating the need to find new design methodologies. In this paper we present a novel SoC co-design methodology based on Model Driven Engineering usi...

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Hauptverfasser: Quadri, I.R., Meftali, S., Dekeyser, J.-L.
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Dekeyser, J.-L.
description As System-on-Chip (SoC) architectures become pivotal for designing embedded systems, the SoC design complexity continues to increase exponentially necessitating the need to find new design methodologies. In this paper we present a novel SoC co-design methodology based on Model Driven Engineering using the MARTE (Modeling and Analysis of Real-time and Embedded Systems) standard. This methodology is utilized to model fine grain reconfigurable architectures such as FPGAs and extends the standard to integrate new features such as Partial Dynamic Reconfiguration supported by modern FPGAs. The goal is to carry out modeling at a high abstraction level expressed in UML (Unified Modeling Language) and following transformations of these models, automatically generate the code necessary for FPGA implementation.
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subjects Application software
Design methodology
Embedded system
Field programmable gate arrays
Hardware
Model driven engineering
Parallel processing
Real time systems
System-on-a-chip
Unified modeling language
title MARTE based modeling approach for Partial Dynamic Reconfigurable FPGAs
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