MARTE based modeling approach for Partial Dynamic Reconfigurable FPGAs
As System-on-Chip (SoC) architectures become pivotal for designing embedded systems, the SoC design complexity continues to increase exponentially necessitating the need to find new design methodologies. In this paper we present a novel SoC co-design methodology based on Model Driven Engineering usi...
Gespeichert in:
Hauptverfasser: | , , |
---|---|
Format: | Tagungsbericht |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | 52 |
---|---|
container_issue | |
container_start_page | 47 |
container_title | |
container_volume | |
creator | Quadri, I.R. Meftali, S. Dekeyser, J.-L. |
description | As System-on-Chip (SoC) architectures become pivotal for designing embedded systems, the SoC design complexity continues to increase exponentially necessitating the need to find new design methodologies. In this paper we present a novel SoC co-design methodology based on Model Driven Engineering using the MARTE (Modeling and Analysis of Real-time and Embedded Systems) standard. This methodology is utilized to model fine grain reconfigurable architectures such as FPGAs and extends the standard to integrate new features such as Partial Dynamic Reconfiguration supported by modern FPGAs. The goal is to carry out modeling at a high abstraction level expressed in UML (Unified Modeling Language) and following transformations of these models, automatically generate the code necessary for FPGA implementation. |
doi_str_mv | 10.1109/ESTMED.2008.4696994 |
format | Conference Proceeding |
fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_4696994</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>4696994</ieee_id><sourcerecordid>4696994</sourcerecordid><originalsourceid>FETCH-LOGICAL-i220t-30d35600fc5b165a9dd42356a3d799e61cf03a550c32f59aae976c726036156e3</originalsourceid><addsrcrecordid>eNotkM1qwkAUhQdaoWp9AjfzAknv3PmJsxRNtKBUrIXu5DozsVNiIold-Pa11LM58HH4FoexsYBUCLAv-ftunc9TBJikylhjrXpgA6FQKTQCPx9ZHyXqRGAmemzwt7OgJhk-sVHXfcMtSssMoM-K9XS7y_mBuuD5qfGhivWR0_ncNuS-eNm0fEPtJVLF59eaTtHxbXBNXcbjT0uHKvBis5h2z6xXUtWF0b2H7KPId7NlsnpbvM6mqyQiwiWR4KU2AKXTB2E0We8V3ghJn1kbjHAlSNIanMRSW6JgM-MyNCCN0CbIIRv_e2MIYX9u44na6_7-gfwFE0dMow</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>MARTE based modeling approach for Partial Dynamic Reconfigurable FPGAs</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Quadri, I.R. ; Meftali, S. ; Dekeyser, J.-L.</creator><creatorcontrib>Quadri, I.R. ; Meftali, S. ; Dekeyser, J.-L.</creatorcontrib><description>As System-on-Chip (SoC) architectures become pivotal for designing embedded systems, the SoC design complexity continues to increase exponentially necessitating the need to find new design methodologies. In this paper we present a novel SoC co-design methodology based on Model Driven Engineering using the MARTE (Modeling and Analysis of Real-time and Embedded Systems) standard. This methodology is utilized to model fine grain reconfigurable architectures such as FPGAs and extends the standard to integrate new features such as Partial Dynamic Reconfiguration supported by modern FPGAs. The goal is to carry out modeling at a high abstraction level expressed in UML (Unified Modeling Language) and following transformations of these models, automatically generate the code necessary for FPGA implementation.</description><identifier>ISSN: 2325-1271</identifier><identifier>ISBN: 142442612X</identifier><identifier>ISBN: 9781424426126</identifier><identifier>DOI: 10.1109/ESTMED.2008.4696994</identifier><identifier>LCCN: 2008904872</identifier><language>eng</language><publisher>IEEE</publisher><subject>Application software ; Design methodology ; Embedded system ; Field programmable gate arrays ; Hardware ; Model driven engineering ; Parallel processing ; Real time systems ; System-on-a-chip ; Unified modeling language</subject><ispartof>2008 IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia, 2008, p.47-52</ispartof><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4696994$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4696994$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Quadri, I.R.</creatorcontrib><creatorcontrib>Meftali, S.</creatorcontrib><creatorcontrib>Dekeyser, J.-L.</creatorcontrib><title>MARTE based modeling approach for Partial Dynamic Reconfigurable FPGAs</title><title>2008 IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia</title><addtitle>ESTMED</addtitle><description>As System-on-Chip (SoC) architectures become pivotal for designing embedded systems, the SoC design complexity continues to increase exponentially necessitating the need to find new design methodologies. In this paper we present a novel SoC co-design methodology based on Model Driven Engineering using the MARTE (Modeling and Analysis of Real-time and Embedded Systems) standard. This methodology is utilized to model fine grain reconfigurable architectures such as FPGAs and extends the standard to integrate new features such as Partial Dynamic Reconfiguration supported by modern FPGAs. The goal is to carry out modeling at a high abstraction level expressed in UML (Unified Modeling Language) and following transformations of these models, automatically generate the code necessary for FPGA implementation.</description><subject>Application software</subject><subject>Design methodology</subject><subject>Embedded system</subject><subject>Field programmable gate arrays</subject><subject>Hardware</subject><subject>Model driven engineering</subject><subject>Parallel processing</subject><subject>Real time systems</subject><subject>System-on-a-chip</subject><subject>Unified modeling language</subject><issn>2325-1271</issn><isbn>142442612X</isbn><isbn>9781424426126</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2008</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotkM1qwkAUhQdaoWp9AjfzAknv3PmJsxRNtKBUrIXu5DozsVNiIold-Pa11LM58HH4FoexsYBUCLAv-ftunc9TBJikylhjrXpgA6FQKTQCPx9ZHyXqRGAmemzwt7OgJhk-sVHXfcMtSssMoM-K9XS7y_mBuuD5qfGhivWR0_ncNuS-eNm0fEPtJVLF59eaTtHxbXBNXcbjT0uHKvBis5h2z6xXUtWF0b2H7KPId7NlsnpbvM6mqyQiwiWR4KU2AKXTB2E0We8V3ghJn1kbjHAlSNIanMRSW6JgM-MyNCCN0CbIIRv_e2MIYX9u44na6_7-gfwFE0dMow</recordid><startdate>20080101</startdate><enddate>20080101</enddate><creator>Quadri, I.R.</creator><creator>Meftali, S.</creator><creator>Dekeyser, J.-L.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>20080101</creationdate><title>MARTE based modeling approach for Partial Dynamic Reconfigurable FPGAs</title><author>Quadri, I.R. ; Meftali, S. ; Dekeyser, J.-L.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i220t-30d35600fc5b165a9dd42356a3d799e61cf03a550c32f59aae976c726036156e3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2008</creationdate><topic>Application software</topic><topic>Design methodology</topic><topic>Embedded system</topic><topic>Field programmable gate arrays</topic><topic>Hardware</topic><topic>Model driven engineering</topic><topic>Parallel processing</topic><topic>Real time systems</topic><topic>System-on-a-chip</topic><topic>Unified modeling language</topic><toplevel>online_resources</toplevel><creatorcontrib>Quadri, I.R.</creatorcontrib><creatorcontrib>Meftali, S.</creatorcontrib><creatorcontrib>Dekeyser, J.-L.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Xplore</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Quadri, I.R.</au><au>Meftali, S.</au><au>Dekeyser, J.-L.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>MARTE based modeling approach for Partial Dynamic Reconfigurable FPGAs</atitle><btitle>2008 IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia</btitle><stitle>ESTMED</stitle><date>2008-01-01</date><risdate>2008</risdate><spage>47</spage><epage>52</epage><pages>47-52</pages><issn>2325-1271</issn><isbn>142442612X</isbn><isbn>9781424426126</isbn><abstract>As System-on-Chip (SoC) architectures become pivotal for designing embedded systems, the SoC design complexity continues to increase exponentially necessitating the need to find new design methodologies. In this paper we present a novel SoC co-design methodology based on Model Driven Engineering using the MARTE (Modeling and Analysis of Real-time and Embedded Systems) standard. This methodology is utilized to model fine grain reconfigurable architectures such as FPGAs and extends the standard to integrate new features such as Partial Dynamic Reconfiguration supported by modern FPGAs. The goal is to carry out modeling at a high abstraction level expressed in UML (Unified Modeling Language) and following transformations of these models, automatically generate the code necessary for FPGA implementation.</abstract><pub>IEEE</pub><doi>10.1109/ESTMED.2008.4696994</doi><tpages>6</tpages><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | ISSN: 2325-1271 |
ispartof | 2008 IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia, 2008, p.47-52 |
issn | 2325-1271 |
language | eng |
recordid | cdi_ieee_primary_4696994 |
source | IEEE Electronic Library (IEL) Conference Proceedings |
subjects | Application software Design methodology Embedded system Field programmable gate arrays Hardware Model driven engineering Parallel processing Real time systems System-on-a-chip Unified modeling language |
title | MARTE based modeling approach for Partial Dynamic Reconfigurable FPGAs |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-01T10%3A23%3A02IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=MARTE%20based%20modeling%20approach%20for%20Partial%20Dynamic%20Reconfigurable%20FPGAs&rft.btitle=2008%20IEEE/ACM/IFIP%20Workshop%20on%20Embedded%20Systems%20for%20Real-Time%20Multimedia&rft.au=Quadri,%20I.R.&rft.date=2008-01-01&rft.spage=47&rft.epage=52&rft.pages=47-52&rft.issn=2325-1271&rft.isbn=142442612X&rft.isbn_list=9781424426126&rft_id=info:doi/10.1109/ESTMED.2008.4696994&rft_dat=%3Cieee_6IE%3E4696994%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=4696994&rfr_iscdi=true |