A T-Coil-Enhanced 8.5 Gb/s High-Swing SST Transmitter in 65 nm Bulk CMOS With ≪ -16 dB Return Loss Over 10 GHz Bandwidth

A source-series-terminated (SST) transmitter in a 65 nm bulk CMOS technology is presented. The circuit exhibits an eye height greater than 1.0 V for data rates of up to 8.5 Gb/s. A thin-oxide pre-driver stage running at 1.0 V drives 22 parallel connected thick-oxide SST output stages operated at 1.5...

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Veröffentlicht in:IEEE journal of solid-state circuits 2008-12, Vol.43 (12), p.2905-2920
Hauptverfasser: Kossel, M., Menolfi, C., Weiss, J., Buchmann, P., von Bueren, G., Rodoni, L., Morf, T., Toifl, T., Schmatz, M.
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container_end_page 2920
container_issue 12
container_start_page 2905
container_title IEEE journal of solid-state circuits
container_volume 43
creator Kossel, M.
Menolfi, C.
Weiss, J.
Buchmann, P.
von Bueren, G.
Rodoni, L.
Morf, T.
Toifl, T.
Schmatz, M.
description A source-series-terminated (SST) transmitter in a 65 nm bulk CMOS technology is presented. The circuit exhibits an eye height greater than 1.0 V for data rates of up to 8.5 Gb/s. A thin-oxide pre-driver stage running at 1.0 V drives 22 parallel connected thick-oxide SST output stages operated at 1.5 V that feature a 5-bit 2-tap FIR filter whose adaptation is independent of the impedance tuning. To achieve a return loss of
doi_str_mv 10.1109/JSSC.2008.2006230
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The circuit exhibits an eye height greater than 1.0 V for data rates of up to 8.5 Gb/s. A thin-oxide pre-driver stage running at 1.0 V drives 22 parallel connected thick-oxide SST output stages operated at 1.5 V that feature a 5-bit 2-tap FIR filter whose adaptation is independent of the impedance tuning. To achieve a return loss of &lt;-16 dB up to 10 GHz a 40 mum times 40 mum T-coil complements the transmitter output. This half-bit-rate clock SST transmitter has a duty-cycle restoration capability of 5x, and the common-mode voltage noise is below 10 mV rms for high-, mid- and low-level terminations. The chip consumes 96 mW at 8.5 Gb/s and occupies 180 mum times 360 mum. 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The circuit exhibits an eye height greater than 1.0 V for data rates of up to 8.5 Gb/s. A thin-oxide pre-driver stage running at 1.0 V drives 22 parallel connected thick-oxide SST output stages operated at 1.5 V that feature a 5-bit 2-tap FIR filter whose adaptation is independent of the impedance tuning. To achieve a return loss of &lt;-16 dB up to 10 GHz a 40 mum times 40 mum T-coil complements the transmitter output. This half-bit-rate clock SST transmitter has a duty-cycle restoration capability of 5x, and the common-mode voltage noise is below 10 mV rms for high-, mid- and low-level terminations. The chip consumes 96 mW at 8.5 Gb/s and occupies 180 mum times 360 mum. In addition to the transmitter design, guidelines for the T-coil design are presented.</description><subject>Applied sciences</subject><subject>Circuit properties</subject><subject>Circuits</subject><subject>Clocks</subject><subject>CMOS technology</subject><subject>De-emphasis</subject><subject>Design. Technologies. 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identifier ISSN: 0018-9200
ispartof IEEE journal of solid-state circuits, 2008-12, Vol.43 (12), p.2905-2920
issn 0018-9200
1558-173X
language eng
recordid cdi_ieee_primary_4684644
source IEEE Electronic Library (IEL)
subjects Applied sciences
Circuit properties
Circuits
Clocks
CMOS technology
De-emphasis
Design. Technologies. Operation analysis. Testing
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
Exact sciences and technology
Finite impulse response filter
Frequency filters
Guidelines
Image restoration
Impedance
impedance tuning
Integrated circuits
Propagation losses
return loss
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
source series termination
T-coil
Transmitters
Voltage
title A T-Coil-Enhanced 8.5 Gb/s High-Swing SST Transmitter in 65 nm Bulk CMOS With ≪ -16 dB Return Loss Over 10 GHz Bandwidth
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