Fully integrated, high performance triple SD PLL (2.2Ghz to 4.4Ghz) with minimized interaction

3 Sigma delta PLLs covering an octave have been integrated on one BiCMOS 0.35 um CSS (channel stacking switch) chip. The 3 PLLs can work simultaneously synthesizing the same frequencies or different frequencies. To minimize the dynamic coupling among the PLLs a complete calibration algorithm has bee...

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Bibliographische Detailangaben
Hauptverfasser:	Cipriani, S., Duvivier, E., Puccio, G., Carpineto, L., Bisanti, B., Coppola, F., Alderton, M., Goldblatt, J.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Algorithm design and analysis BiCMOS BiCMOS integrated circuits Calibration calibration algorithm Cascading style sheets Charge pump CSS Delta-sigma modulation frequency coupling Frequency synthesizers Phase locked loops PLL Satellite communications Sigma delta Stacking Switches Temperature distribution VCO Xtal
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