The 68040 processor. I. Design and implementation
The design of the 68040, a third-generation, full-32-b microprocessor in the Motorola 68000 family, is presented. The 68040 integrates over 1.2 million transistors on one chip and can execute the complete 68020 microprocessor and 68882 floating-point coprocessor instruction sets. Pipelined integer a...
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| Veröffentlicht in: | IEEE MICRO 1990-02, Vol.10 (1), p.66-78 |
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| container_end_page | 78 |
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| container_issue | 1 |
| container_start_page | 66 |
| container_title | IEEE MICRO |
| container_volume | 10 |
| creator | Edenfield, R.W. Gallup, M.G. Ledbetter, W.B. McGarity, R.C. Quintana, E.E. Reininger, R.A. |
| description | The design of the 68040, a third-generation, full-32-b microprocessor in the Motorola 68000 family, is presented. The 68040 integrates over 1.2 million transistors on one chip and can execute the complete 68020 microprocessor and 68882 floating-point coprocessor instruction sets. Pipelined integer and floating-point execution units that operate concurrently with separate internal memory controllers and an autonomous bus controller contribute to its high performance level. Physical caches of 4 kB each for instruction and data reside on chip. Separate address-translation caches of 64 entries apiece operate in parallel with the instruction and data caches. This arrangement provides complete memory management in a virtual, demand-paged operating system. The design team explains its total approach and the workings of the integer and floating-point units.< > |
| doi_str_mv | 10.1109/40.46770 |
| format | Article |
| fullrecord | <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_ieee_primary_46770</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>46770</ieee_id><sourcerecordid>28807327</sourcerecordid><originalsourceid>FETCH-LOGICAL-c1217-2f759b9c0a794c4663d8addad524057440ade739d004200478bb7cc33f13fbf83</originalsourceid><addsrcrecordid>eNo90DtPxDAMB_AIgUQ5kFjZOiGWFufROhnR8TrpJJZjjtLEhaI-jqY38O0pFDFYHvyTZf8Zu-SQcw7mVkGuSkQ4Ygk3EjPFlTxmCQgUGUcpTtlZjB8AUAjQCeO7d0pLDQrS_Th4inEY83STp_cUm7c-dX1Im27fUkf95KZm6M_ZSe3aSBd_fcVeHx926-ds-_K0Wd9tM88Fx0zUWJjKeHBolFdlKYN2IbhQCAUFKgUuEEoTAJSYC3VVofdS1lzWVa3lil0ve-e7Pg8UJ9s10VPbup6GQ7RCa5j_wRneLNCPQ4wj1XY_Np0bvywH-5OJVWB_M5np1UIbIvpny-wbLzBYag</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>28807327</pqid></control><display><type>article</type><title>The 68040 processor. I. Design and implementation</title><source>IEEE/IET Electronic Library (IEL)</source><creator>Edenfield, R.W. ; Gallup, M.G. ; Ledbetter, W.B. ; McGarity, R.C. ; Quintana, E.E. ; Reininger, R.A.</creator><creatorcontrib>Edenfield, R.W. ; Gallup, M.G. ; Ledbetter, W.B. ; McGarity, R.C. ; Quintana, E.E. ; Reininger, R.A.</creatorcontrib><description>The design of the 68040, a third-generation, full-32-b microprocessor in the Motorola 68000 family, is presented. The 68040 integrates over 1.2 million transistors on one chip and can execute the complete 68020 microprocessor and 68882 floating-point coprocessor instruction sets. Pipelined integer and floating-point execution units that operate concurrently with separate internal memory controllers and an autonomous bus controller contribute to its high performance level. Physical caches of 4 kB each for instruction and data reside on chip. Separate address-translation caches of 64 entries apiece operate in parallel with the instruction and data caches. This arrangement provides complete memory management in a virtual, demand-paged operating system. The design team explains its total approach and the workings of the integer and floating-point units.< ></description><identifier>ISSN: 0272-1732</identifier><identifier>EISSN: 1937-4143</identifier><identifier>DOI: 10.1109/40.46770</identifier><identifier>CODEN: IEMIDZ</identifier><language>eng</language><publisher>IEEE</publisher><subject>Clocks ; Coprocessors ; Frequency ; Instruction sets ; Memory management ; Microprocessors ; Operating systems ; Process design ; Silicon ; System-on-a-chip</subject><ispartof>IEEE MICRO, 1990-02, Vol.10 (1), p.66-78</ispartof><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c1217-2f759b9c0a794c4663d8addad524057440ade739d004200478bb7cc33f13fbf83</citedby><cites>FETCH-LOGICAL-c1217-2f759b9c0a794c4663d8addad524057440ade739d004200478bb7cc33f13fbf83</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/46770$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,777,781,793,27905,27906,54739</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/46770$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Edenfield, R.W.</creatorcontrib><creatorcontrib>Gallup, M.G.</creatorcontrib><creatorcontrib>Ledbetter, W.B.</creatorcontrib><creatorcontrib>McGarity, R.C.</creatorcontrib><creatorcontrib>Quintana, E.E.</creatorcontrib><creatorcontrib>Reininger, R.A.</creatorcontrib><title>The 68040 processor. I. Design and implementation</title><title>IEEE MICRO</title><addtitle>MM</addtitle><description>The design of the 68040, a third-generation, full-32-b microprocessor in the Motorola 68000 family, is presented. The 68040 integrates over 1.2 million transistors on one chip and can execute the complete 68020 microprocessor and 68882 floating-point coprocessor instruction sets. Pipelined integer and floating-point execution units that operate concurrently with separate internal memory controllers and an autonomous bus controller contribute to its high performance level. Physical caches of 4 kB each for instruction and data reside on chip. Separate address-translation caches of 64 entries apiece operate in parallel with the instruction and data caches. This arrangement provides complete memory management in a virtual, demand-paged operating system. The design team explains its total approach and the workings of the integer and floating-point units.< ></description><subject>Clocks</subject><subject>Coprocessors</subject><subject>Frequency</subject><subject>Instruction sets</subject><subject>Memory management</subject><subject>Microprocessors</subject><subject>Operating systems</subject><subject>Process design</subject><subject>Silicon</subject><subject>System-on-a-chip</subject><issn>0272-1732</issn><issn>1937-4143</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1990</creationdate><recordtype>article</recordtype><recordid>eNo90DtPxDAMB_AIgUQ5kFjZOiGWFufROhnR8TrpJJZjjtLEhaI-jqY38O0pFDFYHvyTZf8Zu-SQcw7mVkGuSkQ4Ygk3EjPFlTxmCQgUGUcpTtlZjB8AUAjQCeO7d0pLDQrS_Th4inEY83STp_cUm7c-dX1Im27fUkf95KZm6M_ZSe3aSBd_fcVeHx926-ds-_K0Wd9tM88Fx0zUWJjKeHBolFdlKYN2IbhQCAUFKgUuEEoTAJSYC3VVofdS1lzWVa3lil0ve-e7Pg8UJ9s10VPbup6GQ7RCa5j_wRneLNCPQ4wj1XY_Np0bvywH-5OJVWB_M5np1UIbIvpny-wbLzBYag</recordid><startdate>199002</startdate><enddate>199002</enddate><creator>Edenfield, R.W.</creator><creator>Gallup, M.G.</creator><creator>Ledbetter, W.B.</creator><creator>McGarity, R.C.</creator><creator>Quintana, E.E.</creator><creator>Reininger, R.A.</creator><general>IEEE</general><scope>AAYXX</scope><scope>CITATION</scope><scope>7SC</scope><scope>7SP</scope><scope>7U5</scope><scope>8FD</scope><scope>JQ2</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope></search><sort><creationdate>199002</creationdate><title>The 68040 processor. I. Design and implementation</title><author>Edenfield, R.W. ; Gallup, M.G. ; Ledbetter, W.B. ; McGarity, R.C. ; Quintana, E.E. ; Reininger, R.A.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c1217-2f759b9c0a794c4663d8addad524057440ade739d004200478bb7cc33f13fbf83</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1990</creationdate><topic>Clocks</topic><topic>Coprocessors</topic><topic>Frequency</topic><topic>Instruction sets</topic><topic>Memory management</topic><topic>Microprocessors</topic><topic>Operating systems</topic><topic>Process design</topic><topic>Silicon</topic><topic>System-on-a-chip</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Edenfield, R.W.</creatorcontrib><creatorcontrib>Gallup, M.G.</creatorcontrib><creatorcontrib>Ledbetter, W.B.</creatorcontrib><creatorcontrib>McGarity, R.C.</creatorcontrib><creatorcontrib>Quintana, E.E.</creatorcontrib><creatorcontrib>Reininger, R.A.</creatorcontrib><collection>CrossRef</collection><collection>Computer and Information Systems Abstracts</collection><collection>Electronics & Communications Abstracts</collection><collection>Solid State and Superconductivity Abstracts</collection><collection>Technology Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><jtitle>IEEE MICRO</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Edenfield, R.W.</au><au>Gallup, M.G.</au><au>Ledbetter, W.B.</au><au>McGarity, R.C.</au><au>Quintana, E.E.</au><au>Reininger, R.A.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>The 68040 processor. I. Design and implementation</atitle><jtitle>IEEE MICRO</jtitle><stitle>MM</stitle><date>1990-02</date><risdate>1990</risdate><volume>10</volume><issue>1</issue><spage>66</spage><epage>78</epage><pages>66-78</pages><issn>0272-1732</issn><eissn>1937-4143</eissn><coden>IEMIDZ</coden><abstract>The design of the 68040, a third-generation, full-32-b microprocessor in the Motorola 68000 family, is presented. The 68040 integrates over 1.2 million transistors on one chip and can execute the complete 68020 microprocessor and 68882 floating-point coprocessor instruction sets. Pipelined integer and floating-point execution units that operate concurrently with separate internal memory controllers and an autonomous bus controller contribute to its high performance level. Physical caches of 4 kB each for instruction and data reside on chip. Separate address-translation caches of 64 entries apiece operate in parallel with the instruction and data caches. This arrangement provides complete memory management in a virtual, demand-paged operating system. The design team explains its total approach and the workings of the integer and floating-point units.< ></abstract><pub>IEEE</pub><doi>10.1109/40.46770</doi><tpages>13</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 0272-1732 |
| ispartof | IEEE MICRO, 1990-02, Vol.10 (1), p.66-78 |
| issn | 0272-1732 1937-4143 |
| language | eng |
| recordid | cdi_ieee_primary_46770 |
| source | IEEE/IET Electronic Library (IEL) |
| subjects | Clocks Coprocessors Frequency Instruction sets Memory management Microprocessors Operating systems Process design Silicon System-on-a-chip |
| title | The 68040 processor. I. Design and implementation |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-17T16%3A54%3A05IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=The%2068040%20processor.%20I.%20Design%20and%20implementation&rft.jtitle=IEEE%20MICRO&rft.au=Edenfield,%20R.W.&rft.date=1990-02&rft.volume=10&rft.issue=1&rft.spage=66&rft.epage=78&rft.pages=66-78&rft.issn=0272-1732&rft.eissn=1937-4143&rft.coden=IEMIDZ&rft_id=info:doi/10.1109/40.46770&rft_dat=%3Cproquest_RIE%3E28807327%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=28807327&rft_id=info:pmid/&rft_ieee_id=46770&rfr_iscdi=true |