Design of a Two Dimensional PRSI Image Processor
A digital processor capable of computing several two dimensional Position Rotation and Scale Invariant (PRSI) transforms on 64 times 64 pixel images is presented. The architecture is programmable to achieve the following five transforms: Two Dimensional (2D) Fast Fourier Transform (FFT), 2D Log Pola...
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| creator | Tulabandhula, T. Patra, A. Chakrabarti, N.B. |
| description | A digital processor capable of computing several two dimensional Position Rotation and Scale Invariant (PRSI) transforms on 64 times 64 pixel images is presented. The architecture is programmable to achieve the following five transforms: Two Dimensional (2D) Fast Fourier Transform (FFT), 2D Log Polar Transform (LPT), 2D Fourier Mellin Transform (FMT), 2D Analytical Fourier Mellin Transform and Phase only Correlation (POC). 1D FFT design with scale and word-length issues is also detailed. Thirty two 1-Dimensional FFTs have been reused as processing elements in the 2-Dimensional FFT unit. Scheme for matrix transpose in O(N) time is also described. The Image Processor has a word length of 16 bits each for real and imaginary parts and has been implemented on Xilinx Virtex II FPGA. It is capable of processing an image in less than 0.1 ms. |
| doi_str_mv | 10.1109/DSD.2008.80 |
| format | Conference Proceeding |
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The architecture is programmable to achieve the following five transforms: Two Dimensional (2D) Fast Fourier Transform (FFT), 2D Log Polar Transform (LPT), 2D Fourier Mellin Transform (FMT), 2D Analytical Fourier Mellin Transform and Phase only Correlation (POC). 1D FFT design with scale and word-length issues is also detailed. Thirty two 1-Dimensional FFTs have been reused as processing elements in the 2-Dimensional FFT unit. Scheme for matrix transpose in O(N) time is also described. The Image Processor has a word length of 16 bits each for real and imaginary parts and has been implemented on Xilinx Virtex II FPGA. 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It is capable of processing an image in less than 0.1 ms.</description><subject>2D Fast Fourier Transform</subject><subject>AFMT</subject><subject>Application specific integrated circuits</subject><subject>Computer architecture</subject><subject>Coprocessors</subject><subject>Design methodology</subject><subject>Fast Fourier transforms</subject><subject>Field programmable gate arrays</subject><subject>Flexible printed circuits</subject><subject>Fourier Mellin Transform</subject><subject>Hardware</subject><subject>Image Processor</subject><subject>Log Polar Transform</subject><subject>POC</subject><subject>Position Rotation Scale Invariance</subject><subject>Process design</subject><subject>Switches</subject><isbn>9780769532776</isbn><isbn>0769532772</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2008</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotjM1KxDAYRQMyoI5duXSTF2j9ki-_S5n6UxhwcLof0iYZItNGGkF8e0f0Ls5ZHLiE3DJoGAN73-7bhgOYxsAFqaw2oJWVyLVWK3L9WyxXDPGSVKW8w3lCMlRwRaANJR1nmiN1tP_KtE1TmEvKszvR3du-o93kjoHuljyGUvJyQ1bRnUqo_r0m_dNjv3mpt6_P3eZhWyem5WdtvXCDGIWXVoJ36AaJgzOeM8PxzAhCsxhQa20hchMZSvR29FJERI9rcvd3m0IIh48lTW75PgilLEeNPx5AQX4</recordid><startdate>200809</startdate><enddate>200809</enddate><creator>Tulabandhula, T.</creator><creator>Patra, A.</creator><creator>Chakrabarti, N.B.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200809</creationdate><title>Design of a Two Dimensional PRSI Image Processor</title><author>Tulabandhula, T. ; Patra, A. ; Chakrabarti, N.B.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-9d4ab4c4d5950da3ab53ba8d21823d21f0471fe377790f28f1353d9cd54f33d3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2008</creationdate><topic>2D Fast Fourier Transform</topic><topic>AFMT</topic><topic>Application specific integrated circuits</topic><topic>Computer architecture</topic><topic>Coprocessors</topic><topic>Design methodology</topic><topic>Fast Fourier transforms</topic><topic>Field programmable gate arrays</topic><topic>Flexible printed circuits</topic><topic>Fourier Mellin Transform</topic><topic>Hardware</topic><topic>Image Processor</topic><topic>Log Polar Transform</topic><topic>POC</topic><topic>Position Rotation Scale Invariance</topic><topic>Process design</topic><topic>Switches</topic><toplevel>online_resources</toplevel><creatorcontrib>Tulabandhula, T.</creatorcontrib><creatorcontrib>Patra, A.</creatorcontrib><creatorcontrib>Chakrabarti, N.B.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Tulabandhula, T.</au><au>Patra, A.</au><au>Chakrabarti, N.B.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Design of a Two Dimensional PRSI Image Processor</atitle><btitle>2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools</btitle><stitle>DSD</stitle><date>2008-09</date><risdate>2008</risdate><spage>195</spage><epage>202</epage><pages>195-202</pages><isbn>9780769532776</isbn><isbn>0769532772</isbn><abstract>A digital processor capable of computing several two dimensional Position Rotation and Scale Invariant (PRSI) transforms on 64 times 64 pixel images is presented. The architecture is programmable to achieve the following five transforms: Two Dimensional (2D) Fast Fourier Transform (FFT), 2D Log Polar Transform (LPT), 2D Fourier Mellin Transform (FMT), 2D Analytical Fourier Mellin Transform and Phase only Correlation (POC). 1D FFT design with scale and word-length issues is also detailed. Thirty two 1-Dimensional FFTs have been reused as processing elements in the 2-Dimensional FFT unit. Scheme for matrix transpose in O(N) time is also described. The Image Processor has a word length of 16 bits each for real and imaginary parts and has been implemented on Xilinx Virtex II FPGA. It is capable of processing an image in less than 0.1 ms.</abstract><pub>IEEE</pub><doi>10.1109/DSD.2008.80</doi><tpages>8</tpages></addata></record> |
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| identifier | ISBN: 9780769532776 |
| ispartof | 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools, 2008, p.195-202 |
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| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | 2D Fast Fourier Transform AFMT Application specific integrated circuits Computer architecture Coprocessors Design methodology Fast Fourier transforms Field programmable gate arrays Flexible printed circuits Fourier Mellin Transform Hardware Image Processor Log Polar Transform POC Position Rotation Scale Invariance Process design Switches |
| title | Design of a Two Dimensional PRSI Image Processor |
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