An FPGA-based digital class-D amplifier using short word-length

A digital Class-D amplifier based on single-bit processing to be implemented on a field programmable gate array (FPGA) is presented. The main focus of this design is the reduction of noise, a drawback of Class-D amplifiers, by exploring the noise-shaping characteristics of sigma-delta modulation (SD...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Thakkar, D., Lethbridge, G., Targownik, T., Ling, A., Sadik, A.Z., Beckett, P., Hussain, Z.M.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Class-D Delta-sigma modulation Digital signal processing Field programmable gate arrays FPGA Multi-stage noise shaping Noise reduction Noise shaping Pulse amplifiers Pulse width modulation Quantization Sigma-Delta Modulation Space vector pulse width modulation VHDL
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