Module Grouping for Defect Tolerance in Nanoscale Memory
Designing a nanoscale memory system with defect rate as high as 10% poses a significant challenge. Redundancies at various levels have been employed to tolerate the high defect rates. Multiple crossbar modules that share the same address space can be used to build a simple and robust memory architec...
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| creator | Yoonjae Huh Yoon-Hwa Choi |
| description | Designing a nanoscale memory system with defect rate as high as 10% poses a significant challenge. Redundancies at various levels have been employed to tolerate the high defect rates. Multiple crossbar modules that share the same address space can be used to build a simple and robust memory architecture to overcome the defects in the crossbar. In this paper, we presents a module grouping scheme for tolerating defects in a nanoscale memory composed of nano-modules. Redundancy at nano-module level with some degree of flexibility in assigning nano-modules is used to achieve defect tolerance. Computer simulation shows that the proposed scheme can construct a functioning memory with up to 45% reduction in the required number of nano-modules as compared to the existing simple redundancy scheme. |
| doi_str_mv | 10.1109/DFT.2008.47 |
| format | Conference Proceeding |
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Redundancies at various levels have been employed to tolerate the high defect rates. Multiple crossbar modules that share the same address space can be used to build a simple and robust memory architecture to overcome the defects in the crossbar. In this paper, we presents a module grouping scheme for tolerating defects in a nanoscale memory composed of nano-modules. Redundancy at nano-module level with some degree of flexibility in assigning nano-modules is used to achieve defect tolerance. Computer simulation shows that the proposed scheme can construct a functioning memory with up to 45% reduction in the required number of nano-modules as compared to the existing simple redundancy scheme.</description><identifier>ISSN: 1550-5774</identifier><identifier>ISBN: 0769533655</identifier><identifier>ISBN: 9780769533650</identifier><identifier>EISSN: 2377-7966</identifier><identifier>DOI: 10.1109/DFT.2008.47</identifier><language>eng</language><publisher>IEEE</publisher><subject>Computer simulation ; Decoding ; defect tolerance ; Indexes ; Memory management ; module grouping ; Nanoscale devices ; nanoscale memory ; Redundancy ; Strontium</subject><ispartof>2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems, 2008, p.16-23</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4641153$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4641153$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Yoonjae Huh</creatorcontrib><creatorcontrib>Yoon-Hwa Choi</creatorcontrib><title>Module Grouping for Defect Tolerance in Nanoscale Memory</title><title>2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems</title><addtitle>DFTVS</addtitle><description>Designing a nanoscale memory system with defect rate as high as 10% poses a significant challenge. Redundancies at various levels have been employed to tolerate the high defect rates. Multiple crossbar modules that share the same address space can be used to build a simple and robust memory architecture to overcome the defects in the crossbar. In this paper, we presents a module grouping scheme for tolerating defects in a nanoscale memory composed of nano-modules. Redundancy at nano-module level with some degree of flexibility in assigning nano-modules is used to achieve defect tolerance. Computer simulation shows that the proposed scheme can construct a functioning memory with up to 45% reduction in the required number of nano-modules as compared to the existing simple redundancy scheme.</description><subject>Computer simulation</subject><subject>Decoding</subject><subject>defect tolerance</subject><subject>Indexes</subject><subject>Memory management</subject><subject>module grouping</subject><subject>Nanoscale devices</subject><subject>nanoscale memory</subject><subject>Redundancy</subject><subject>Strontium</subject><issn>1550-5774</issn><issn>2377-7966</issn><isbn>0769533655</isbn><isbn>9780769533650</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2008</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotj7tOw0AQAE88JExIRUnjH7DZe-36SpSQgJRAY-rozrdGRo4vspMif08kqKYZjTRCPEoopQT3vFzVpQKoSkNXIlOaqCCHeC3ugdBZrdHaG5FJa6GwROZOzKfpBwCkQwLnMlFtUzz1nK_HdDp0w3fepjFfcsvNMa9Tz6MfGs67If_wQ5oaf1G3vE_j-UHctr6feP7PmfhavdaLt2LzuX5fvGyKTpI9FsE6rxEAtSeK0Qa0VeCKlFaoYnAGI2AItgGJTdRKVYq1pCCNUpGD1DPx9NftmHl3GLu9H887g0bKy98vaGVGAg</recordid><startdate>200810</startdate><enddate>200810</enddate><creator>Yoonjae Huh</creator><creator>Yoon-Hwa Choi</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200810</creationdate><title>Module Grouping for Defect Tolerance in Nanoscale Memory</title><author>Yoonjae Huh ; Yoon-Hwa Choi</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-b59a360063a77dd5b658be8723262db946d06bb5c016cd32282e317b1422deb13</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2008</creationdate><topic>Computer simulation</topic><topic>Decoding</topic><topic>defect tolerance</topic><topic>Indexes</topic><topic>Memory management</topic><topic>module grouping</topic><topic>Nanoscale devices</topic><topic>nanoscale memory</topic><topic>Redundancy</topic><topic>Strontium</topic><toplevel>online_resources</toplevel><creatorcontrib>Yoonjae Huh</creatorcontrib><creatorcontrib>Yoon-Hwa Choi</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Yoonjae Huh</au><au>Yoon-Hwa Choi</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Module Grouping for Defect Tolerance in Nanoscale Memory</atitle><btitle>2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems</btitle><stitle>DFTVS</stitle><date>2008-10</date><risdate>2008</risdate><spage>16</spage><epage>23</epage><pages>16-23</pages><issn>1550-5774</issn><eissn>2377-7966</eissn><isbn>0769533655</isbn><isbn>9780769533650</isbn><abstract>Designing a nanoscale memory system with defect rate as high as 10% poses a significant challenge. Redundancies at various levels have been employed to tolerate the high defect rates. Multiple crossbar modules that share the same address space can be used to build a simple and robust memory architecture to overcome the defects in the crossbar. In this paper, we presents a module grouping scheme for tolerating defects in a nanoscale memory composed of nano-modules. Redundancy at nano-module level with some degree of flexibility in assigning nano-modules is used to achieve defect tolerance. Computer simulation shows that the proposed scheme can construct a functioning memory with up to 45% reduction in the required number of nano-modules as compared to the existing simple redundancy scheme.</abstract><pub>IEEE</pub><doi>10.1109/DFT.2008.47</doi><tpages>8</tpages></addata></record> |
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| ispartof | 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems, 2008, p.16-23 |
| issn | 1550-5774 2377-7966 |
| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Computer simulation Decoding defect tolerance Indexes Memory management module grouping Nanoscale devices nanoscale memory Redundancy Strontium |
| title | Module Grouping for Defect Tolerance in Nanoscale Memory |
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