A single SiGe chip fractional-N 275 MHz - 20 GHz PLL with integrated 20 GHz VCO
Broad band satellite communication makes high demands on linear low phase noise signals. One example is HDTV. For this application converters are required (e.g. from 30 GHz to 20 GHz), which themselves require very low phase noise programmable synthesizers (LO). Most satellite companies today derive...
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creator | Follmann, R. Kother, D. Kohl, T. Engels, M. Podrebersek, T. Heyer, V. Schmalz, K. Herzel, F. Winkler, W. Osmany, S. Jagdhold, U. |
description | Broad band satellite communication makes high demands on linear low phase noise signals. One example is HDTV. For this application converters are required (e.g. from 30 GHz to 20 GHz), which themselves require very low phase noise programmable synthesizers (LO). Most satellite companies today derive their 10 GHz LOs from multiplying a 100 MHz crystal oscillator again and again. Due to the arising sub-harmonics excessive filtering is required. Thus, today's satellite LOs are large and quite heavy in weight. In this paper we demonstrate a single chip SiGe integrated fractional-N PLL, which can either be used with the internal integrated VCO between 18.5 and 20.0 GHz or with any external VCO between 275 MHz...20 GHz. The LO presented fulfills the high demands on phase noise for satellite applications. Furthermore, first radiation hardness steps such as triple model redundancy have already been implemented. |
doi_str_mv | 10.1109/MWSYM.2008.4633176 |
format | Conference Proceeding |
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One example is HDTV. For this application converters are required (e.g. from 30 GHz to 20 GHz), which themselves require very low phase noise programmable synthesizers (LO). Most satellite companies today derive their 10 GHz LOs from multiplying a 100 MHz crystal oscillator again and again. Due to the arising sub-harmonics excessive filtering is required. Thus, today's satellite LOs are large and quite heavy in weight. In this paper we demonstrate a single chip SiGe integrated fractional-N PLL, which can either be used with the internal integrated VCO between 18.5 and 20.0 GHz or with any external VCO between 275 MHz...20 GHz. The LO presented fulfills the high demands on phase noise for satellite applications. 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One example is HDTV. For this application converters are required (e.g. from 30 GHz to 20 GHz), which themselves require very low phase noise programmable synthesizers (LO). Most satellite companies today derive their 10 GHz LOs from multiplying a 100 MHz crystal oscillator again and again. Due to the arising sub-harmonics excessive filtering is required. Thus, today's satellite LOs are large and quite heavy in weight. In this paper we demonstrate a single chip SiGe integrated fractional-N PLL, which can either be used with the internal integrated VCO between 18.5 and 20.0 GHz or with any external VCO between 275 MHz...20 GHz. The LO presented fulfills the high demands on phase noise for satellite applications. Furthermore, first radiation hardness steps such as triple model redundancy have already been implemented.</description><subject>CMOS</subject><subject>Connectors</subject><subject>downconverter</subject><subject>mixed signal</subject><subject>Phase locked loops</subject><subject>Phase noise</subject><subject>PLL</subject><subject>Radiation detectors</subject><subject>satellite applications</subject><subject>Satellites</subject><subject>SiGe</subject><subject>Silicon germanium</subject><subject>synthesizer</subject><subject>VCO</subject><subject>Voltage-controlled oscillators</subject><issn>0149-645X</issn><issn>2576-7216</issn><isbn>1424417805</isbn><isbn>9781424417803</isbn><isbn>9781424417810</isbn><isbn>1424417813</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2008</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNp9j8tOwkAUQC8KiUX4AdzcH5hy73Qe7dIQhQUVEozKikxggCGlkraJ0a8XE9i6Oic5qwMwYIqZKRvm74tlHkuiNFYmSdiaFvQzm7KSSvGZdAOR1NYIK9ncQvcaSLchIlaZMEp_dCCy9s9Y6jvo1vWBiHTKJoLZI9ah3BUeF2Hscb0PJ9xWbt2Ez9IV4gWl1ZhPflCgJByfZT6d4ldo9hjKxu8q1_jNNb2NZj3obF1R-_6F9_Dw_PQ6mojgvV-dqnB01ffqMpP8X38BcdpBzg</recordid><startdate>200806</startdate><enddate>200806</enddate><creator>Follmann, R.</creator><creator>Kother, D.</creator><creator>Kohl, T.</creator><creator>Engels, M.</creator><creator>Podrebersek, T.</creator><creator>Heyer, V.</creator><creator>Schmalz, K.</creator><creator>Herzel, F.</creator><creator>Winkler, W.</creator><creator>Osmany, S.</creator><creator>Jagdhold, U.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>200806</creationdate><title>A single SiGe chip fractional-N 275 MHz - 20 GHz PLL with integrated 20 GHz VCO</title><author>Follmann, R. ; Kother, D. ; Kohl, T. ; Engels, M. ; Podrebersek, T. ; Heyer, V. ; Schmalz, K. ; Herzel, F. ; Winkler, W. ; Osmany, S. ; Jagdhold, U.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-ieee_primary_46331763</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2008</creationdate><topic>CMOS</topic><topic>Connectors</topic><topic>downconverter</topic><topic>mixed signal</topic><topic>Phase locked loops</topic><topic>Phase noise</topic><topic>PLL</topic><topic>Radiation detectors</topic><topic>satellite applications</topic><topic>Satellites</topic><topic>SiGe</topic><topic>Silicon germanium</topic><topic>synthesizer</topic><topic>VCO</topic><topic>Voltage-controlled oscillators</topic><toplevel>online_resources</toplevel><creatorcontrib>Follmann, R.</creatorcontrib><creatorcontrib>Kother, D.</creatorcontrib><creatorcontrib>Kohl, T.</creatorcontrib><creatorcontrib>Engels, M.</creatorcontrib><creatorcontrib>Podrebersek, T.</creatorcontrib><creatorcontrib>Heyer, V.</creatorcontrib><creatorcontrib>Schmalz, K.</creatorcontrib><creatorcontrib>Herzel, F.</creatorcontrib><creatorcontrib>Winkler, W.</creatorcontrib><creatorcontrib>Osmany, S.</creatorcontrib><creatorcontrib>Jagdhold, U.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Follmann, R.</au><au>Kother, D.</au><au>Kohl, T.</au><au>Engels, M.</au><au>Podrebersek, T.</au><au>Heyer, V.</au><au>Schmalz, K.</au><au>Herzel, F.</au><au>Winkler, W.</au><au>Osmany, S.</au><au>Jagdhold, U.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A single SiGe chip fractional-N 275 MHz - 20 GHz PLL with integrated 20 GHz VCO</atitle><btitle>2008 IEEE MTT-S International Microwave Symposium Digest</btitle><stitle>MWSYM</stitle><date>2008-06</date><risdate>2008</risdate><spage>355</spage><epage>358</epage><pages>355-358</pages><issn>0149-645X</issn><eissn>2576-7216</eissn><isbn>1424417805</isbn><isbn>9781424417803</isbn><eisbn>9781424417810</eisbn><eisbn>1424417813</eisbn><abstract>Broad band satellite communication makes high demands on linear low phase noise signals. One example is HDTV. For this application converters are required (e.g. from 30 GHz to 20 GHz), which themselves require very low phase noise programmable synthesizers (LO). Most satellite companies today derive their 10 GHz LOs from multiplying a 100 MHz crystal oscillator again and again. Due to the arising sub-harmonics excessive filtering is required. Thus, today's satellite LOs are large and quite heavy in weight. In this paper we demonstrate a single chip SiGe integrated fractional-N PLL, which can either be used with the internal integrated VCO between 18.5 and 20.0 GHz or with any external VCO between 275 MHz...20 GHz. The LO presented fulfills the high demands on phase noise for satellite applications. Furthermore, first radiation hardness steps such as triple model redundancy have already been implemented.</abstract><pub>IEEE</pub><doi>10.1109/MWSYM.2008.4633176</doi></addata></record> |
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ispartof | 2008 IEEE MTT-S International Microwave Symposium Digest, 2008, p.355-358 |
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language | eng |
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source | IEEE Electronic Library (IEL) Conference Proceedings |
subjects | CMOS Connectors downconverter mixed signal Phase locked loops Phase noise PLL Radiation detectors satellite applications Satellites SiGe Silicon germanium synthesizer VCO Voltage-controlled oscillators |
title | A single SiGe chip fractional-N 275 MHz - 20 GHz PLL with integrated 20 GHz VCO |
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