Novel FPGA based Haar classifier face detection algorithm acceleration

We present here a novel approach to use FPGA to accelerate the Haar-classifier based face detection algorithm. With highly pipelined microarchitecture and utilizing abundant parallel arithmetic units in the FPGA, we've achieved real-time performance of face detection having very high detection...

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Hauptverfasser:	Changjian Gao, Shih-Lien Lu
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Classification algorithms Fabrics Face Face detection Field programmable gate arrays Pixel Software
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creator	Changjian Gao Shih-Lien Lu
description	We present here a novel approach to use FPGA to accelerate the Haar-classifier based face detection algorithm. With highly pipelined microarchitecture and utilizing abundant parallel arithmetic units in the FPGA, we've achieved real-time performance of face detection having very high detection rate and low false positives. Moreover, our approach is flexible toward the resources available on the FPGA chip. This work also provides us an understanding toward using FPGA for implementing non-systolic based vision algorithm acceleration. Our implementation is realized on a HiTech Global PCIe card that contains a Xilinx XC5VLX110T FPGA chip.
doi_str_mv	10.1109/FPL.2008.4629966
format	Conference Proceeding
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identifier	ISSN: 1946-147X
ispartof	2008 International Conference on Field Programmable Logic and Applications, 2008, p.373-378
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language	eng
recordid	cdi_ieee_primary_4629966
source	IEEE Electronic Library (IEL) Conference Proceedings
subjects	Classification algorithms Fabrics Face Face detection Field programmable gate arrays Pixel Software
title	Novel FPGA based Haar classifier face detection algorithm acceleration
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