A synchronous modular multiplier with variable latency
Modular multiplication is a very important arithmetic operation in cryptography systems and residue-based computation. This paper presents a synchronous modular multiplier that has variable computation latency depending on operand values. The modular reduction operation is based on SRT radix-2 divis...
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| creator | Kuan Jen Lin Yen Hung Lin |
| description | Modular multiplication is a very important arithmetic operation in cryptography systems and residue-based computation. This paper presents a synchronous modular multiplier that has variable computation latency depending on operand values. The modular reduction operation is based on SRT radix-2 division. However, the quotient selection function in certain stages is adapted for reducing delay and area. The proposed variable latency design was synthesized and verified with TSMC 0.18 mum technology. It can achieve significant computation time reduction compared to a fixed-latency design, while needing only 4 % larger area. |
| doi_str_mv | 10.1109/MWSCAS.2008.4616800 |
| format | Conference Proceeding |
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This paper presents a synchronous modular multiplier that has variable computation latency depending on operand values. The modular reduction operation is based on SRT radix-2 division. However, the quotient selection function in certain stages is adapted for reducing delay and area. The proposed variable latency design was synthesized and verified with TSMC 0.18 mum technology. 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This paper presents a synchronous modular multiplier that has variable computation latency depending on operand values. The modular reduction operation is based on SRT radix-2 division. However, the quotient selection function in certain stages is adapted for reducing delay and area. The proposed variable latency design was synthesized and verified with TSMC 0.18 mum technology. It can achieve significant computation time reduction compared to a fixed-latency design, while needing only 4 % larger area.</description><subject>Algorithm design and analysis</subject><subject>Cryptography</subject><subject>Delay</subject><subject>Equations</subject><subject>Hardware</subject><subject>Logic gates</subject><subject>Signal processing algorithms</subject><issn>1548-3746</issn><issn>1558-3899</issn><isbn>9781424421664</isbn><isbn>1424421667</isbn><isbn>1424421675</isbn><isbn>9781424421671</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2008</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNo1j0lOwzAYhc0k0ZaeoBtfIMHD72kZRVCQilgUxLJyHEc1cpIqAyi3J4iyeW_xSW9AaENJSikx9y8f-zzbp4wQnYKkUhNygZYUGACjUolLtKBC6IRrY67Q2ij9zyRc_zKYmQJ5i5Z9_0kI44qaBZIZ7qfGHbu2acce1205RtvheoxDOMXgO_wdhiP-sl2wRfQ42sE3brpDN5WNvV-ffYXeHx_e8qdk97p9zrNdEqgSQwJCEyoKpTWb-2zJiJvFAQcPpfNKFMJxqTlAwRy3BlxVlFC5eRupTOn5Cm3-coP3_nDqQm276XD-z38A4ohLIw</recordid><startdate>200808</startdate><enddate>200808</enddate><creator>Kuan Jen Lin</creator><creator>Yen Hung Lin</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>200808</creationdate><title>A synchronous modular multiplier with variable latency</title><author>Kuan Jen Lin ; Yen Hung Lin</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-458015b7882237ad20cad2c434e4dce75b5c368344b2c3a94cfbd4fc3710f9de3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2008</creationdate><topic>Algorithm design and analysis</topic><topic>Cryptography</topic><topic>Delay</topic><topic>Equations</topic><topic>Hardware</topic><topic>Logic gates</topic><topic>Signal processing algorithms</topic><toplevel>online_resources</toplevel><creatorcontrib>Kuan Jen Lin</creatorcontrib><creatorcontrib>Yen Hung Lin</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Kuan Jen Lin</au><au>Yen Hung Lin</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A synchronous modular multiplier with variable latency</atitle><btitle>2008 51st Midwest Symposium on Circuits and Systems</btitle><stitle>MWSCAS</stitle><date>2008-08</date><risdate>2008</risdate><spage>318</spage><epage>321</epage><pages>318-321</pages><issn>1548-3746</issn><eissn>1558-3899</eissn><isbn>9781424421664</isbn><isbn>1424421667</isbn><eisbn>1424421675</eisbn><eisbn>9781424421671</eisbn><abstract>Modular multiplication is a very important arithmetic operation in cryptography systems and residue-based computation. This paper presents a synchronous modular multiplier that has variable computation latency depending on operand values. The modular reduction operation is based on SRT radix-2 division. However, the quotient selection function in certain stages is adapted for reducing delay and area. The proposed variable latency design was synthesized and verified with TSMC 0.18 mum technology. It can achieve significant computation time reduction compared to a fixed-latency design, while needing only 4 % larger area.</abstract><pub>IEEE</pub><doi>10.1109/MWSCAS.2008.4616800</doi><tpages>4</tpages></addata></record> |
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| ispartof | 2008 51st Midwest Symposium on Circuits and Systems, 2008, p.318-321 |
| issn | 1548-3746 1558-3899 |
| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Algorithm design and analysis Cryptography Delay Equations Hardware Logic gates Signal processing algorithms |
| title | A synchronous modular multiplier with variable latency |
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