Phase-frequency synthesis using PLL-networks
Conventional phase locked loop (PLL)-networks used for phase synthesis lack accurate frequency controllability. We describe a novel phase-frequency synthesizer architecture based on coupled-PLLs suitable for communication systems. We also present the phase noise analysis of the proposed architecture...
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| creator | Iyer, S.P.A. Oliaei, O. |
| description | Conventional phase locked loop (PLL)-networks used for phase synthesis lack accurate frequency controllability. We describe a novel phase-frequency synthesizer architecture based on coupled-PLLs suitable for communication systems. We also present the phase noise analysis of the proposed architecture and demonstrate its superior phase noise performance compared with conventional coupled-PLLs. |
| doi_str_mv | 10.1109/NEWCAS.2008.4606307 |
| format | Conference Proceeding |
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We describe a novel phase-frequency synthesizer architecture based on coupled-PLLs suitable for communication systems. We also present the phase noise analysis of the proposed architecture and demonstrate its superior phase noise performance compared with conventional coupled-PLLs.</description><subject>Arrays</subject><subject>Charge pumps</subject><subject>Frequency synthesizers</subject><subject>Phase frequency detector</subject><subject>Phase locked loops</subject><subject>Phase noise</subject><subject>Voltage-controlled oscillators</subject><isbn>9781424423316</isbn><isbn>1424423317</isbn><isbn>9781424423323</isbn><isbn>1424423325</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2008</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpVj9tKw0AURUekoNZ8QV_yAU48Z-bM7bGEeoFgC1V8LEk8sfESNZMi-Xsr9sX9stiw2LCFmCFkiBAu7xaP-XydKQCfkQWrwR2JJDiPpIiU1kof_-toJ-LsVw-gPJkTkcT4AvuQ2ctwKi5W2zKybHr-2nFXj2kcu2HLsY3pLrbdc7oqCtnx8P3Rv8ZzMWnKt8jJgVPxcLW4z29ksby-zeeFbNGZQWpn0ZgamZyzFRlLWltVlQG9hydCx8orDFiaWkODXCFA1biGQm0JjddTMfvbbZl589m372U_bg6H9Q9EhkTW</recordid><startdate>200806</startdate><enddate>200806</enddate><creator>Iyer, S.P.A.</creator><creator>Oliaei, O.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200806</creationdate><title>Phase-frequency synthesis using PLL-networks</title><author>Iyer, S.P.A. ; Oliaei, O.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-376155c1e4776b45643362ba91880d417e282191a5c30f1eb100bf7f49c641583</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2008</creationdate><topic>Arrays</topic><topic>Charge pumps</topic><topic>Frequency synthesizers</topic><topic>Phase frequency detector</topic><topic>Phase locked loops</topic><topic>Phase noise</topic><topic>Voltage-controlled oscillators</topic><toplevel>online_resources</toplevel><creatorcontrib>Iyer, S.P.A.</creatorcontrib><creatorcontrib>Oliaei, O.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Iyer, S.P.A.</au><au>Oliaei, O.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Phase-frequency synthesis using PLL-networks</atitle><btitle>2008 Joint 6th International IEEE Northeast Workshop on Circuits and Systems and TAISA Conference</btitle><stitle>NEWCAS</stitle><date>2008-06</date><risdate>2008</risdate><spage>5</spage><epage>8</epage><pages>5-8</pages><isbn>9781424423316</isbn><isbn>1424423317</isbn><eisbn>9781424423323</eisbn><eisbn>1424423325</eisbn><abstract>Conventional phase locked loop (PLL)-networks used for phase synthesis lack accurate frequency controllability. We describe a novel phase-frequency synthesizer architecture based on coupled-PLLs suitable for communication systems. We also present the phase noise analysis of the proposed architecture and demonstrate its superior phase noise performance compared with conventional coupled-PLLs.</abstract><pub>IEEE</pub><doi>10.1109/NEWCAS.2008.4606307</doi><tpages>4</tpages></addata></record> |
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| ispartof | 2008 Joint 6th International IEEE Northeast Workshop on Circuits and Systems and TAISA Conference, 2008, p.5-8 |
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| language | eng |
| recordid | cdi_ieee_primary_4606307 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Arrays Charge pumps Frequency synthesizers Phase frequency detector Phase locked loops Phase noise Voltage-controlled oscillators |
| title | Phase-frequency synthesis using PLL-networks |
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