Effect of single grain boundary position on surrounding-gate polysilicon thin film transistors

In this paper, single-grain-boundary-position-induced electrical characteristic variations in 300 nm surrounding-gate (i.e, gate-all-around, GAA) polysilicon thin film transistors (TFTs) are numerically investigated. For a 2T1C active-matrix circuit, a three-dimensional device-circuit coupled mixed-...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Yiming Li, Huang, J.Y., Bo-Shian Lee, Chih-Hong Hwang
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Calibrated trap model parameters Device circuit mixed-mode simulation Electron traps Grain boundaries Logic gates Mathematical model Organic light emitting diodes Polysilicon TFT Position of single grain boundary Surrounding-gate Thin film transistors Threshold voltage
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