Effect of single grain boundary position on surrounding-gate polysilicon thin film transistors
In this paper, single-grain-boundary-position-induced electrical characteristic variations in 300 nm surrounding-gate (i.e, gate-all-around, GAA) polysilicon thin film transistors (TFTs) are numerically investigated. For a 2T1C active-matrix circuit, a three-dimensional device-circuit coupled mixed-...
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| creator | Yiming Li Huang, J.Y. Bo-Shian Lee Chih-Hong Hwang |
| description | In this paper, single-grain-boundary-position-induced electrical characteristic variations in 300 nm surrounding-gate (i.e, gate-all-around, GAA) polysilicon thin film transistors (TFTs) are numerically investigated. For a 2T1C active-matrix circuit, a three-dimensional device-circuit coupled mixed-mode simulation shows that the switching speed of GAA TFT can be improved by nine times, compared with the result of the circuit using single-gate (SG) polysilicon TFTs. The position of single grain boundary near the drain side has an ill effect on device performance, but the influence can be suppressed in the GAA polysilicon TFTs. We found that under the same threshold voltage, the variation of threshold voltage can be reduced from 15 % to 5 %, with varying of gate structures of the GAA polysilicon TFT. |
| doi_str_mv | 10.1109/NANO.2007.4601386 |
| format | Conference Proceeding |
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For a 2T1C active-matrix circuit, a three-dimensional device-circuit coupled mixed-mode simulation shows that the switching speed of GAA TFT can be improved by nine times, compared with the result of the circuit using single-gate (SG) polysilicon TFTs. The position of single grain boundary near the drain side has an ill effect on device performance, but the influence can be suppressed in the GAA polysilicon TFTs. We found that under the same threshold voltage, the variation of threshold voltage can be reduced from 15 % to 5 %, with varying of gate structures of the GAA polysilicon TFT.</description><identifier>ISSN: 1944-9399</identifier><identifier>ISBN: 9781424406074</identifier><identifier>ISBN: 1424406072</identifier><identifier>EISSN: 1944-9380</identifier><identifier>EISBN: 9781424406081</identifier><identifier>EISBN: 1424406080</identifier><identifier>DOI: 10.1109/NANO.2007.4601386</identifier><identifier>LCCN: 200693137</identifier><language>eng</language><publisher>IEEE</publisher><subject>Calibrated trap model parameters ; Device circuit mixed-mode simulation ; Electron traps ; Grain boundaries ; Logic gates ; Mathematical model ; Organic light emitting diodes ; Polysilicon TFT ; Position of single grain boundary ; Surrounding-gate ; Thin film transistors ; Threshold voltage</subject><ispartof>2007 7th IEEE Conference on Nanotechnology (IEEE NANO), 2007, p.1148-1151</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4601386$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,27902,54895</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4601386$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Yiming Li</creatorcontrib><creatorcontrib>Huang, J.Y.</creatorcontrib><creatorcontrib>Bo-Shian Lee</creatorcontrib><creatorcontrib>Chih-Hong Hwang</creatorcontrib><title>Effect of single grain boundary position on surrounding-gate polysilicon thin film transistors</title><title>2007 7th IEEE Conference on Nanotechnology (IEEE NANO)</title><addtitle>NANO</addtitle><description>In this paper, single-grain-boundary-position-induced electrical characteristic variations in 300 nm surrounding-gate (i.e, gate-all-around, GAA) polysilicon thin film transistors (TFTs) are numerically investigated. For a 2T1C active-matrix circuit, a three-dimensional device-circuit coupled mixed-mode simulation shows that the switching speed of GAA TFT can be improved by nine times, compared with the result of the circuit using single-gate (SG) polysilicon TFTs. The position of single grain boundary near the drain side has an ill effect on device performance, but the influence can be suppressed in the GAA polysilicon TFTs. We found that under the same threshold voltage, the variation of threshold voltage can be reduced from 15 % to 5 %, with varying of gate structures of the GAA polysilicon TFT.</description><subject>Calibrated trap model parameters</subject><subject>Device circuit mixed-mode simulation</subject><subject>Electron traps</subject><subject>Grain boundaries</subject><subject>Logic gates</subject><subject>Mathematical model</subject><subject>Organic light emitting diodes</subject><subject>Polysilicon TFT</subject><subject>Position of single grain boundary</subject><subject>Surrounding-gate</subject><subject>Thin film transistors</subject><subject>Threshold voltage</subject><issn>1944-9399</issn><issn>1944-9380</issn><isbn>9781424406074</isbn><isbn>1424406072</isbn><isbn>9781424406081</isbn><isbn>1424406080</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2007</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpVkMtqwzAQRdVHoGmaDyjd6Afsjh6WrGUI6QNCsmjXDX6MXBXHDpKyyN9XpaFQuDBwz8xluITcM8gZA_O4WWy2OQfQuVTARKkuyNzokkkuJSgo2SWZMiNlZkQJV_-Yltd_zJgJmaYYZQQT-obchvAFwIFrNiUfK2uxiXS0NLih65F2vnIDrcfj0Fb-RA9jcNGNA00KR-9__LSYdVXEBPtTcL1rEoyf6cy6fk-jr4bgQhx9uCMTW_UB5-c5I29Pq_flS7bePr8uF-vMGYgZSmVqYWtZN6gLDkXNOZbAdMG05bxRiEIgcImyEKIVTasMaBBSKcMqLmbk4TfVIeLu4N0-fb47lya-AcmvWtE</recordid><startdate>200708</startdate><enddate>200708</enddate><creator>Yiming Li</creator><creator>Huang, J.Y.</creator><creator>Bo-Shian Lee</creator><creator>Chih-Hong Hwang</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>200708</creationdate><title>Effect of single grain boundary position on surrounding-gate polysilicon thin film transistors</title><author>Yiming Li ; Huang, J.Y. ; Bo-Shian Lee ; Chih-Hong Hwang</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-e469b3fb4bce75205b22e8017517f22c6ee33e024e4533d3cd69070346691a23</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2007</creationdate><topic>Calibrated trap model parameters</topic><topic>Device circuit mixed-mode simulation</topic><topic>Electron traps</topic><topic>Grain boundaries</topic><topic>Logic gates</topic><topic>Mathematical model</topic><topic>Organic light emitting diodes</topic><topic>Polysilicon TFT</topic><topic>Position of single grain boundary</topic><topic>Surrounding-gate</topic><topic>Thin film transistors</topic><topic>Threshold voltage</topic><toplevel>online_resources</toplevel><creatorcontrib>Yiming Li</creatorcontrib><creatorcontrib>Huang, J.Y.</creatorcontrib><creatorcontrib>Bo-Shian Lee</creatorcontrib><creatorcontrib>Chih-Hong Hwang</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Yiming Li</au><au>Huang, J.Y.</au><au>Bo-Shian Lee</au><au>Chih-Hong Hwang</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Effect of single grain boundary position on surrounding-gate polysilicon thin film transistors</atitle><btitle>2007 7th IEEE Conference on Nanotechnology (IEEE NANO)</btitle><stitle>NANO</stitle><date>2007-08</date><risdate>2007</risdate><spage>1148</spage><epage>1151</epage><pages>1148-1151</pages><issn>1944-9399</issn><eissn>1944-9380</eissn><isbn>9781424406074</isbn><isbn>1424406072</isbn><eisbn>9781424406081</eisbn><eisbn>1424406080</eisbn><abstract>In this paper, single-grain-boundary-position-induced electrical characteristic variations in 300 nm surrounding-gate (i.e, gate-all-around, GAA) polysilicon thin film transistors (TFTs) are numerically investigated. For a 2T1C active-matrix circuit, a three-dimensional device-circuit coupled mixed-mode simulation shows that the switching speed of GAA TFT can be improved by nine times, compared with the result of the circuit using single-gate (SG) polysilicon TFTs. The position of single grain boundary near the drain side has an ill effect on device performance, but the influence can be suppressed in the GAA polysilicon TFTs. We found that under the same threshold voltage, the variation of threshold voltage can be reduced from 15 % to 5 %, with varying of gate structures of the GAA polysilicon TFT.</abstract><pub>IEEE</pub><doi>10.1109/NANO.2007.4601386</doi><tpages>4</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 1944-9399 |
| ispartof | 2007 7th IEEE Conference on Nanotechnology (IEEE NANO), 2007, p.1148-1151 |
| issn | 1944-9399 1944-9380 |
| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Calibrated trap model parameters Device circuit mixed-mode simulation Electron traps Grain boundaries Logic gates Mathematical model Organic light emitting diodes Polysilicon TFT Position of single grain boundary Surrounding-gate Thin film transistors Threshold voltage |
| title | Effect of single grain boundary position on surrounding-gate polysilicon thin film transistors |
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