Address generator realization using completely-specified Boolean functions

We are proposing a cost-efficient realization scheme for completely-specified logic functions characterized by a huge disproportion. The functions described contain millions of input words but only few of them can give us information. An appropriate method of logic synthesis for identifying mentione...

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Bibliographische Detailangaben

Hauptverfasser:	Borowik, G., Majchrzyk, M., Darakchiev, R.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Address generator Decomposition Embedded memory Finite state machine FPGA Logic cell Logic synthesis
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