Address generator realization using completely-specified Boolean functions
We are proposing a cost-efficient realization scheme for completely-specified logic functions characterized by a huge disproportion. The functions described contain millions of input words but only few of them can give us information. An appropriate method of logic synthesis for identifying mentione...
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| creator | Borowik, G. Majchrzyk, M. Darakchiev, R. |
| description | We are proposing a cost-efficient realization scheme for completely-specified logic functions characterized by a huge disproportion. The functions described contain millions of input words but only few of them can give us information. An appropriate method of logic synthesis for identifying mentioned vectors (registered vectors) has been developed. In this method logic functions are implemented using both embedded memory blocks and LUT-based programmable logic blocks available in today's FPGAs. The paper presents the results of our research. In comparison with the classical logic synthesis methods and other dedicated methods we have obtained extremely encouraging results: with a comparable number of EMBs, the number of logic cells has been reduced by 95%. The investigation has been implemented using Altera's Stratix devices. |
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The functions described contain millions of input words but only few of them can give us information. An appropriate method of logic synthesis for identifying mentioned vectors (registered vectors) has been developed. In this method logic functions are implemented using both embedded memory blocks and LUT-based programmable logic blocks available in today's FPGAs. The paper presents the results of our research. In comparison with the classical logic synthesis methods and other dedicated methods we have obtained extremely encouraging results: with a comparable number of EMBs, the number of logic cells has been reduced by 95%. The investigation has been implemented using Altera's Stratix devices.</description><identifier>ISBN: 8392263278</identifier><identifier>ISBN: 9788392263272</identifier><identifier>EISBN: 9788392263289</identifier><identifier>EISBN: 8392263286</identifier><language>eng</language><publisher>IEEE</publisher><subject>Address generator ; Decomposition ; Embedded memory ; Finite state machine ; FPGA ; Logic cell ; Logic synthesis</subject><ispartof>2008 15th International Conference on Mixed Design of Integrated Circuits and Systems, 2008, p.187-192</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4600891$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,54898</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4600891$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Borowik, G.</creatorcontrib><creatorcontrib>Majchrzyk, M.</creatorcontrib><creatorcontrib>Darakchiev, R.</creatorcontrib><title>Address generator realization using completely-specified Boolean functions</title><title>2008 15th International Conference on Mixed Design of Integrated Circuits and Systems</title><addtitle>MIXDES</addtitle><description>We are proposing a cost-efficient realization scheme for completely-specified logic functions characterized by a huge disproportion. The functions described contain millions of input words but only few of them can give us information. An appropriate method of logic synthesis for identifying mentioned vectors (registered vectors) has been developed. In this method logic functions are implemented using both embedded memory blocks and LUT-based programmable logic blocks available in today's FPGAs. The paper presents the results of our research. In comparison with the classical logic synthesis methods and other dedicated methods we have obtained extremely encouraging results: with a comparable number of EMBs, the number of logic cells has been reduced by 95%. The investigation has been implemented using Altera's Stratix devices.</description><subject>Address generator</subject><subject>Decomposition</subject><subject>Embedded memory</subject><subject>Finite state machine</subject><subject>FPGA</subject><subject>Logic cell</subject><subject>Logic synthesis</subject><isbn>8392263278</isbn><isbn>9788392263272</isbn><isbn>9788392263289</isbn><isbn>8392263286</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2008</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNo1j8tKAzEYhSNSUNt5Ajd5gYE_l8llWYtXCm50XTKTPyUyTYZkuqhPb4u6Onxw-A7nijRWGyMs50pwY6_J3T9oc0OaWr8AgFmlQXa35G3tfcFa6R4TFjfnQgu6MX67OeZEjzWmPR3yYRpxxvHU1gmHGCJ6-pDziC7RcEzDpVtXZBHcWLH5yyX5fHr82Ly02_fn181620amu7m1ppMez-tWMOE5ojAgwGphLOt6BZqBZcAC19hpybXoXegV7wO73JIoluT-1xsRcTeVeHDltJMK4GwQP_LJSC8</recordid><startdate>200806</startdate><enddate>200806</enddate><creator>Borowik, G.</creator><creator>Majchrzyk, M.</creator><creator>Darakchiev, R.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200806</creationdate><title>Address generator realization using completely-specified Boolean functions</title><author>Borowik, G. ; Majchrzyk, M. ; Darakchiev, R.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-9854de7049313d2ee380309738915b607109101f27e574273bafb62bf178834e3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2008</creationdate><topic>Address generator</topic><topic>Decomposition</topic><topic>Embedded memory</topic><topic>Finite state machine</topic><topic>FPGA</topic><topic>Logic cell</topic><topic>Logic synthesis</topic><toplevel>online_resources</toplevel><creatorcontrib>Borowik, G.</creatorcontrib><creatorcontrib>Majchrzyk, M.</creatorcontrib><creatorcontrib>Darakchiev, R.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Borowik, G.</au><au>Majchrzyk, M.</au><au>Darakchiev, R.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Address generator realization using completely-specified Boolean functions</atitle><btitle>2008 15th International Conference on Mixed Design of Integrated Circuits and Systems</btitle><stitle>MIXDES</stitle><date>2008-06</date><risdate>2008</risdate><spage>187</spage><epage>192</epage><pages>187-192</pages><isbn>8392263278</isbn><isbn>9788392263272</isbn><eisbn>9788392263289</eisbn><eisbn>8392263286</eisbn><abstract>We are proposing a cost-efficient realization scheme for completely-specified logic functions characterized by a huge disproportion. The functions described contain millions of input words but only few of them can give us information. An appropriate method of logic synthesis for identifying mentioned vectors (registered vectors) has been developed. In this method logic functions are implemented using both embedded memory blocks and LUT-based programmable logic blocks available in today's FPGAs. The paper presents the results of our research. In comparison with the classical logic synthesis methods and other dedicated methods we have obtained extremely encouraging results: with a comparable number of EMBs, the number of logic cells has been reduced by 95%. The investigation has been implemented using Altera's Stratix devices.</abstract><pub>IEEE</pub><tpages>6</tpages></addata></record> |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Address generator Decomposition Embedded memory Finite state machine FPGA Logic cell Logic synthesis |
| title | Address generator realization using completely-specified Boolean functions |
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