A method to design ternary multiplexers controlled by ternary signals based on SUS-LOC

In this paper, a method to design ternary multiplexers with any number of inputs is presented. The basic circuit used to design all ternary multiplexers is the 3-to-1 multiplexer. Starting from the basic multiplexer in binary, we design and simulate the 3-to-1 multiplexer. The multiplexer is built w...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Sipos, E., Oltean, G., Miron, C.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Biological system modeling Design methodology Integrated circuit modeling Inverters Logic gates Multiplexing Transistors
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!