Functional verification of digital circuits using a software system
The process of functional verification used in electronic design automation implies checking that the logic design conforms to its specifications. A verification environment is built to provide scenarios to be checked. The simulation environment contains the following blocks: generator (generates in...
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| creator | Rancea, I. Sgarciu, V. |
| description | The process of functional verification used in electronic design automation implies checking that the logic design conforms to its specifications. A verification environment is built to provide scenarios to be checked. The simulation environment contains the following blocks: generator (generates inputs), driver translates the input stimuli provided by the generator into input for the design under verification (DUT), score-boards database (simulates the correct behavior of the DUT and is used as reference for the verification), and different metrics of coverage. Another target of the functional verification besides checking the equivalence between DUT behavior and its specification is to obtain 100% coverage. The coverage plan is represented by the sum of all scenarios on which the DUT will be exposed. |
| doi_str_mv | 10.1109/AQTR.2008.4588725 |
| format | Conference Proceeding |
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The coverage plan is represented by the sum of all scenarios on which the DUT will be exposed.</description><subject>chip design</subject><subject>code reuse</subject><subject>coverage plan</subject><subject>digital circuits</subject><subject>Driver circuits</subject><subject>Engines</subject><subject>Generators</subject><subject>Monitoring</subject><subject>Protocols</subject><subject>simulation</subject><subject>Testing</subject><subject>verification</subject><subject>Writing</subject><isbn>9781424425761</isbn><isbn>142442576X</isbn><isbn>9781424425778</isbn><isbn>1424425778</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2008</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpVUMtKAzEUjUhBrfMB4iY_MGOSm-eyFKtCQZS6LiG5UyLtjEwySv_eKXbj2RzOgwv3EHLHWcM5cw-Lt817IxizjVTWGqEuSOWM5VJIKZQx9vKf1nxGbk51x6SU-opUOX-yCVKBcuKaLFdjF0rqO7-n3zikNgV_krRvaUy7VCY_pCGMqWQ65tTtqKe5b8uPH5DmYy54uCWz1u8zVmeek4_V42b5XK9fn16Wi3WduFGljtqiBAdMSJheAaaDwiiQe80COKlDZAHRQAteSKt5O6WgogfujHER5uT-725CxO3XkA5-OG7PO8AvNLNOYg</recordid><startdate>200805</startdate><enddate>200805</enddate><creator>Rancea, I.</creator><creator>Sgarciu, V.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200805</creationdate><title>Functional verification of digital circuits using a software system</title><author>Rancea, I. ; Sgarciu, V.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-d68e43930243109306c5ed2e1a60c3946cd0cee73f3a24861fed235da319779d3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2008</creationdate><topic>chip design</topic><topic>code reuse</topic><topic>coverage plan</topic><topic>digital circuits</topic><topic>Driver circuits</topic><topic>Engines</topic><topic>Generators</topic><topic>Monitoring</topic><topic>Protocols</topic><topic>simulation</topic><topic>Testing</topic><topic>verification</topic><topic>Writing</topic><toplevel>online_resources</toplevel><creatorcontrib>Rancea, I.</creatorcontrib><creatorcontrib>Sgarciu, V.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Rancea, I.</au><au>Sgarciu, V.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Functional verification of digital circuits using a software system</atitle><btitle>2008 IEEE International Conference on Automation, Quality and Testing, Robotics</btitle><stitle>AQTR</stitle><date>2008-05</date><risdate>2008</risdate><volume>1</volume><spage>152</spage><epage>157</epage><pages>152-157</pages><isbn>9781424425761</isbn><isbn>142442576X</isbn><eisbn>9781424425778</eisbn><eisbn>1424425778</eisbn><abstract>The process of functional verification used in electronic design automation implies checking that the logic design conforms to its specifications. A verification environment is built to provide scenarios to be checked. The simulation environment contains the following blocks: generator (generates inputs), driver translates the input stimuli provided by the generator into input for the design under verification (DUT), score-boards database (simulates the correct behavior of the DUT and is used as reference for the verification), and different metrics of coverage. Another target of the functional verification besides checking the equivalence between DUT behavior and its specification is to obtain 100% coverage. The coverage plan is represented by the sum of all scenarios on which the DUT will be exposed.</abstract><pub>IEEE</pub><doi>10.1109/AQTR.2008.4588725</doi><tpages>6</tpages></addata></record> |
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| subjects | chip design code reuse coverage plan digital circuits Driver circuits Engines Generators Monitoring Protocols simulation Testing verification Writing |
| title | Functional verification of digital circuits using a software system |
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