Laser-annealed junctions with advanced CMOS gate stacks for 32nm Node: Perspectives on device performance and manufacturability
In this paper, we report on the integration of laser-annealed junctions into a state-of-the-art high-k/metal gate process flow. After implant optimization, we achieve excellent Lg scaling of 15/30 nm over a spike reference, for nMOS and pMOS respectively, without any performance loss. This enables t...
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| creator | Ortolland, C. Noda, T. Chiarella, T. Kubicek, S. Kerner, C. Vandervorst, W. Opdebeeck, A. Vrancken, C. Horiguchi, N. De Potter, M. Aoulaiche, M. Rosseel, E. Felch, S.B. Absil, P. Schreutelkamp, R. Biesemans, S. Hoffmann, T. |
| description | In this paper, we report on the integration of laser-annealed junctions into a state-of-the-art high-k/metal gate process flow. After implant optimization, we achieve excellent Lg scaling of 15/30 nm over a spike reference, for nMOS and pMOS respectively, without any performance loss. This enables to fabricate transistors with Lg min meeting the 32 nm node requirement. In addition, we highlight the implication of the metal gate integration flow (ldquogate-firstrdquo vs. ldquogate-lastrdquo) on the junctions design. Also, we demonstrate that a millisecond anneal only (MSA-only) process can fulfill even the stringent junction leakage requirement for low power applications. Finally, based on a combination of physical and electrical characterization, we show for the very first time that micro-uniformities specific to this diffusion-less process have a negligible electrical impact in nominal devices. |
| doi_str_mv | 10.1109/VLSIT.2008.4588612 |
| format | Conference Proceeding |
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After implant optimization, we achieve excellent Lg scaling of 15/30 nm over a spike reference, for nMOS and pMOS respectively, without any performance loss. This enables to fabricate transistors with Lg min meeting the 32 nm node requirement. In addition, we highlight the implication of the metal gate integration flow (ldquogate-firstrdquo vs. ldquogate-lastrdquo) on the junctions design. Also, we demonstrate that a millisecond anneal only (MSA-only) process can fulfill even the stringent junction leakage requirement for low power applications. Finally, based on a combination of physical and electrical characterization, we show for the very first time that micro-uniformities specific to this diffusion-less process have a negligible electrical impact in nominal devices.</description><identifier>ISSN: 0743-1562</identifier><identifier>ISBN: 142441802X</identifier><identifier>ISBN: 9781424418022</identifier><identifier>EISBN: 9781424418039</identifier><identifier>EISBN: 1424418038</identifier><identifier>DOI: 10.1109/VLSIT.2008.4588612</identifier><identifier>LCCN: 90-655131</identifier><language>eng</language><publisher>IEEE</publisher><subject>Annealing ; Implants ; Junctions ; Lasers ; Logic gates ; MOS devices ; Semiconductor lasers</subject><ispartof>2008 Symposium on VLSI Technology, 2008, p.186-187</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4588612$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,27902,54895</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4588612$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Ortolland, C.</creatorcontrib><creatorcontrib>Noda, T.</creatorcontrib><creatorcontrib>Chiarella, T.</creatorcontrib><creatorcontrib>Kubicek, S.</creatorcontrib><creatorcontrib>Kerner, C.</creatorcontrib><creatorcontrib>Vandervorst, W.</creatorcontrib><creatorcontrib>Opdebeeck, A.</creatorcontrib><creatorcontrib>Vrancken, C.</creatorcontrib><creatorcontrib>Horiguchi, N.</creatorcontrib><creatorcontrib>De Potter, M.</creatorcontrib><creatorcontrib>Aoulaiche, M.</creatorcontrib><creatorcontrib>Rosseel, E.</creatorcontrib><creatorcontrib>Felch, S.B.</creatorcontrib><creatorcontrib>Absil, P.</creatorcontrib><creatorcontrib>Schreutelkamp, R.</creatorcontrib><creatorcontrib>Biesemans, S.</creatorcontrib><creatorcontrib>Hoffmann, T.</creatorcontrib><title>Laser-annealed junctions with advanced CMOS gate stacks for 32nm Node: Perspectives on device performance and manufacturability</title><title>2008 Symposium on VLSI Technology</title><addtitle>VLSIT</addtitle><description>In this paper, we report on the integration of laser-annealed junctions into a state-of-the-art high-k/metal gate process flow. After implant optimization, we achieve excellent Lg scaling of 15/30 nm over a spike reference, for nMOS and pMOS respectively, without any performance loss. This enables to fabricate transistors with Lg min meeting the 32 nm node requirement. In addition, we highlight the implication of the metal gate integration flow (ldquogate-firstrdquo vs. ldquogate-lastrdquo) on the junctions design. Also, we demonstrate that a millisecond anneal only (MSA-only) process can fulfill even the stringent junction leakage requirement for low power applications. Finally, based on a combination of physical and electrical characterization, we show for the very first time that micro-uniformities specific to this diffusion-less process have a negligible electrical impact in nominal devices.</description><subject>Annealing</subject><subject>Implants</subject><subject>Junctions</subject><subject>Lasers</subject><subject>Logic gates</subject><subject>MOS devices</subject><subject>Semiconductor lasers</subject><issn>0743-1562</issn><isbn>142441802X</isbn><isbn>9781424418022</isbn><isbn>9781424418039</isbn><isbn>1424418038</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2008</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNo1UMtOwzAQNIJKlNIfgIt_IMXPOOaGKh6VCkVqhbhVG3sDLq1TxWlRT_w6QcBKq5kdzcxhCbngbMQ5s1cv0_lkMRKMFSOliyLn4ogMrSm4Ekrxgkl7TM7-D_F6QvrMKJlxnYse6VuW5VpzyU_JMKUV60Zpya3pk68pJGwyiBFhjZ6udtG1oY6Jfob2nYLfQ3SdPn6czekbtEhTC-4j0apuqBRxQ59qj9f0GZu0xS66x0TrSD3ug0O6xaYzbn46KERPO7arwLW7BsqwDu3hnPQqWCcc_uGALO5uF-OHbDq7n4xvplmwrM0qaUC6biUoo7wweQG6ZLxCKJmACozPwTlTCmULX7nc6VLm2kkjuJVayAG5_K0NiLjcNmEDzWH590r5DX5HZcE</recordid><startdate>200806</startdate><enddate>200806</enddate><creator>Ortolland, C.</creator><creator>Noda, T.</creator><creator>Chiarella, T.</creator><creator>Kubicek, S.</creator><creator>Kerner, C.</creator><creator>Vandervorst, W.</creator><creator>Opdebeeck, A.</creator><creator>Vrancken, C.</creator><creator>Horiguchi, N.</creator><creator>De Potter, M.</creator><creator>Aoulaiche, M.</creator><creator>Rosseel, E.</creator><creator>Felch, S.B.</creator><creator>Absil, P.</creator><creator>Schreutelkamp, R.</creator><creator>Biesemans, S.</creator><creator>Hoffmann, T.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>200806</creationdate><title>Laser-annealed junctions with advanced CMOS gate stacks for 32nm Node: Perspectives on device performance and manufacturability</title><author>Ortolland, C. ; Noda, T. ; Chiarella, T. ; Kubicek, S. ; Kerner, C. ; Vandervorst, W. ; Opdebeeck, A. ; Vrancken, C. ; Horiguchi, N. ; De Potter, M. ; Aoulaiche, M. ; Rosseel, E. ; Felch, S.B. ; Absil, P. ; Schreutelkamp, R. ; Biesemans, S. ; Hoffmann, T.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-f37a3c7a33a474d2768a5b01feab02afa7d6acc7b2498dfc6c5b365c372193523</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2008</creationdate><topic>Annealing</topic><topic>Implants</topic><topic>Junctions</topic><topic>Lasers</topic><topic>Logic gates</topic><topic>MOS devices</topic><topic>Semiconductor lasers</topic><toplevel>online_resources</toplevel><creatorcontrib>Ortolland, C.</creatorcontrib><creatorcontrib>Noda, T.</creatorcontrib><creatorcontrib>Chiarella, T.</creatorcontrib><creatorcontrib>Kubicek, S.</creatorcontrib><creatorcontrib>Kerner, C.</creatorcontrib><creatorcontrib>Vandervorst, W.</creatorcontrib><creatorcontrib>Opdebeeck, A.</creatorcontrib><creatorcontrib>Vrancken, C.</creatorcontrib><creatorcontrib>Horiguchi, N.</creatorcontrib><creatorcontrib>De Potter, M.</creatorcontrib><creatorcontrib>Aoulaiche, M.</creatorcontrib><creatorcontrib>Rosseel, E.</creatorcontrib><creatorcontrib>Felch, S.B.</creatorcontrib><creatorcontrib>Absil, P.</creatorcontrib><creatorcontrib>Schreutelkamp, R.</creatorcontrib><creatorcontrib>Biesemans, S.</creatorcontrib><creatorcontrib>Hoffmann, T.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Ortolland, C.</au><au>Noda, T.</au><au>Chiarella, T.</au><au>Kubicek, S.</au><au>Kerner, C.</au><au>Vandervorst, W.</au><au>Opdebeeck, A.</au><au>Vrancken, C.</au><au>Horiguchi, N.</au><au>De Potter, M.</au><au>Aoulaiche, M.</au><au>Rosseel, E.</au><au>Felch, S.B.</au><au>Absil, P.</au><au>Schreutelkamp, R.</au><au>Biesemans, S.</au><au>Hoffmann, T.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Laser-annealed junctions with advanced CMOS gate stacks for 32nm Node: Perspectives on device performance and manufacturability</atitle><btitle>2008 Symposium on VLSI Technology</btitle><stitle>VLSIT</stitle><date>2008-06</date><risdate>2008</risdate><spage>186</spage><epage>187</epage><pages>186-187</pages><issn>0743-1562</issn><isbn>142441802X</isbn><isbn>9781424418022</isbn><eisbn>9781424418039</eisbn><eisbn>1424418038</eisbn><abstract>In this paper, we report on the integration of laser-annealed junctions into a state-of-the-art high-k/metal gate process flow. After implant optimization, we achieve excellent Lg scaling of 15/30 nm over a spike reference, for nMOS and pMOS respectively, without any performance loss. This enables to fabricate transistors with Lg min meeting the 32 nm node requirement. In addition, we highlight the implication of the metal gate integration flow (ldquogate-firstrdquo vs. ldquogate-lastrdquo) on the junctions design. Also, we demonstrate that a millisecond anneal only (MSA-only) process can fulfill even the stringent junction leakage requirement for low power applications. Finally, based on a combination of physical and electrical characterization, we show for the very first time that micro-uniformities specific to this diffusion-less process have a negligible electrical impact in nominal devices.</abstract><pub>IEEE</pub><doi>10.1109/VLSIT.2008.4588612</doi><tpages>2</tpages></addata></record> |
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| ispartof | 2008 Symposium on VLSI Technology, 2008, p.186-187 |
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| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Annealing Implants Junctions Lasers Logic gates MOS devices Semiconductor lasers |
| title | Laser-annealed junctions with advanced CMOS gate stacks for 32nm Node: Perspectives on device performance and manufacturability |
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