Novel and cost-efficient single metallic silicide integration solution with dual Schottky-barrier achieved by aluminum inter-diffusion for FinFET CMOS technology with enhanced performance
We have developed a novel and cost-efficient silicide integration solution to achieve a hole barrier height of 215 meV and electron barrier height of 665 meV simultaneously with a single metallic silicide based on aluminum inter-diffusion. It is proposed that aluminum diffuses into PtSi and forms an...
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| creator | Lee, R.T-P. Koh, A.T-Y. Wei-Wei Fang Kian-Ming Tan Lim, A.E-J. Tsung-Yang Liow Chow Shue-Yin Yong, A.M. Hoong Shing Wong Guo-Qiang Lo Samudra, G.S. Dong-Zhi Chi Yee-Chia Yeo |
| description | We have developed a novel and cost-efficient silicide integration solution to achieve a hole barrier height of 215 meV and electron barrier height of 665 meV simultaneously with a single metallic silicide based on aluminum inter-diffusion. It is proposed that aluminum diffuses into PtSi and forms an alloy, which lowers the electron barrier height of PtSi due to a change in the intrinsic PtSi workfunction. Additionally, we have integrated platinum germanosilicide with an ultra-low hole barrier height of 215 meV in P-FinFETs to provide a 21% enhancement in drive current performance, which is attributed to the 20% reduction in series resistance. We have also ascertained the compatibility of PtSiGe with laser thermal annealing for further performance enhancement. |
| doi_str_mv | 10.1109/VLSIT.2008.4588551 |
| format | Conference Proceeding |
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It is proposed that aluminum diffuses into PtSi and forms an alloy, which lowers the electron barrier height of PtSi due to a change in the intrinsic PtSi workfunction. Additionally, we have integrated platinum germanosilicide with an ultra-low hole barrier height of 215 meV in P-FinFETs to provide a 21% enhancement in drive current performance, which is attributed to the 20% reduction in series resistance. We have also ascertained the compatibility of PtSiGe with laser thermal annealing for further performance enhancement.</description><subject>Annealing</subject><subject>FinFETs</subject><subject>Performance evaluation</subject><subject>Resistance</subject><subject>Silicides</subject><subject>Silicon</subject><subject>Silicon germanium</subject><issn>0743-1562</issn><isbn>142441802X</isbn><isbn>9781424418022</isbn><isbn>9781424418039</isbn><isbn>1424418038</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2008</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNo1kU1OwzAQhY0AiQK9AGx8gRTbsRN7iSp-KhW6aIXYIceZNAbHqRynqGfjcqS0zGLmPWnet5hB6IaSCaVE3b3Nl7PVhBEiJ1xIKQQ9QWOVS8oZ51SSVJ2iy3_D3s_QiOQ8TajI2DkaKZJkQySlF2jcdZ9kKC5SqvIR-nltt-Cw9iU2bRcTqCprLPiIO-vXDnADUTtnzeCHbkvA1kdYBx1t63HXuv5PfNtY47LXDi9N3cb4tUsKHYKFgLWpLWyhxMUOa9c31vfNHyQkpa2qvtvnqzbgR-sfH1Z4-rJY4gim9q1r17sDGnytvRkgGwjDbrM31-i80q6D8XFeodWQnz4n88XTbHo_T6wiMSkEI1JkSsuMKZNyQyrGhKRZmYFiUIiCakMLklMui-HCKS9UqY1RIjclzfL0Ct0esBYAPjbBNjrsPo5vSH8BMil8Zg</recordid><startdate>200806</startdate><enddate>200806</enddate><creator>Lee, R.T-P.</creator><creator>Koh, A.T-Y.</creator><creator>Wei-Wei Fang</creator><creator>Kian-Ming Tan</creator><creator>Lim, A.E-J.</creator><creator>Tsung-Yang Liow</creator><creator>Chow Shue-Yin</creator><creator>Yong, A.M.</creator><creator>Hoong Shing Wong</creator><creator>Guo-Qiang Lo</creator><creator>Samudra, G.S.</creator><creator>Dong-Zhi Chi</creator><creator>Yee-Chia Yeo</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>200806</creationdate><title>Novel and cost-efficient single metallic silicide integration solution with dual Schottky-barrier achieved by aluminum inter-diffusion for FinFET CMOS technology with enhanced performance</title><author>Lee, R.T-P. ; Koh, A.T-Y. ; Wei-Wei Fang ; Kian-Ming Tan ; Lim, A.E-J. ; Tsung-Yang Liow ; Chow Shue-Yin ; Yong, A.M. ; Hoong Shing Wong ; Guo-Qiang Lo ; Samudra, G.S. ; Dong-Zhi Chi ; Yee-Chia Yeo</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-b5208569a8629c34c0f225816d6e92eb5b1ac1b07148b20034b9dacc957cd1673</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2008</creationdate><topic>Annealing</topic><topic>FinFETs</topic><topic>Performance evaluation</topic><topic>Resistance</topic><topic>Silicides</topic><topic>Silicon</topic><topic>Silicon germanium</topic><toplevel>online_resources</toplevel><creatorcontrib>Lee, R.T-P.</creatorcontrib><creatorcontrib>Koh, A.T-Y.</creatorcontrib><creatorcontrib>Wei-Wei Fang</creatorcontrib><creatorcontrib>Kian-Ming Tan</creatorcontrib><creatorcontrib>Lim, A.E-J.</creatorcontrib><creatorcontrib>Tsung-Yang Liow</creatorcontrib><creatorcontrib>Chow Shue-Yin</creatorcontrib><creatorcontrib>Yong, A.M.</creatorcontrib><creatorcontrib>Hoong Shing Wong</creatorcontrib><creatorcontrib>Guo-Qiang Lo</creatorcontrib><creatorcontrib>Samudra, G.S.</creatorcontrib><creatorcontrib>Dong-Zhi Chi</creatorcontrib><creatorcontrib>Yee-Chia Yeo</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Lee, R.T-P.</au><au>Koh, A.T-Y.</au><au>Wei-Wei Fang</au><au>Kian-Ming Tan</au><au>Lim, A.E-J.</au><au>Tsung-Yang Liow</au><au>Chow Shue-Yin</au><au>Yong, A.M.</au><au>Hoong Shing Wong</au><au>Guo-Qiang Lo</au><au>Samudra, G.S.</au><au>Dong-Zhi Chi</au><au>Yee-Chia Yeo</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Novel and cost-efficient single metallic silicide integration solution with dual Schottky-barrier achieved by aluminum inter-diffusion for FinFET CMOS technology with enhanced performance</atitle><btitle>2008 Symposium on VLSI Technology</btitle><stitle>VLSIT</stitle><date>2008-06</date><risdate>2008</risdate><spage>28</spage><epage>29</epage><pages>28-29</pages><issn>0743-1562</issn><isbn>142441802X</isbn><isbn>9781424418022</isbn><eisbn>9781424418039</eisbn><eisbn>1424418038</eisbn><abstract>We have developed a novel and cost-efficient silicide integration solution to achieve a hole barrier height of 215 meV and electron barrier height of 665 meV simultaneously with a single metallic silicide based on aluminum inter-diffusion. It is proposed that aluminum diffuses into PtSi and forms an alloy, which lowers the electron barrier height of PtSi due to a change in the intrinsic PtSi workfunction. Additionally, we have integrated platinum germanosilicide with an ultra-low hole barrier height of 215 meV in P-FinFETs to provide a 21% enhancement in drive current performance, which is attributed to the 20% reduction in series resistance. We have also ascertained the compatibility of PtSiGe with laser thermal annealing for further performance enhancement.</abstract><pub>IEEE</pub><doi>10.1109/VLSIT.2008.4588551</doi><tpages>2</tpages></addata></record> |
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| identifier | ISSN: 0743-1562 |
| ispartof | 2008 Symposium on VLSI Technology, 2008, p.28-29 |
| issn | 0743-1562 |
| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Annealing FinFETs Performance evaluation Resistance Silicides Silicon Silicon germanium |
| title | Novel and cost-efficient single metallic silicide integration solution with dual Schottky-barrier achieved by aluminum inter-diffusion for FinFET CMOS technology with enhanced performance |
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