A teraBit/s-throughput, SerDes-based interface for a third-generation 16 core 32 thread chip-multithreading SPARC processor
Third-generation 16 core 32 thread chip-multithreading SPARC processor interface has 1.1 Tbps I/O throughput with 112 Tx/176 Rx SerDes channels in 46 mm 2 . Individual links run at BER of 1E-12 on FR4 PCBs at 4.08-0.5 Gbps full-half rate, and 18 mW/ch/Gbps at 2.67 Gbps. Each link has linear equaliza...
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| creator | Nasrullah, J. Amin, A. Ahmad, W. Zuxu Qin Mushtaq, Z. Javed, O. Joon Yoon Chua, L. Dawei Huang Baoqing Huang Vichare, M. Ho, K. Rashid, M. |
| description | Third-generation 16 core 32 thread chip-multithreading SPARC processor interface has 1.1 Tbps I/O throughput with 112 Tx/176 Rx SerDes channels in 46 mm 2 . Individual links run at BER of 1E-12 on FR4 PCBs at 4.08-0.5 Gbps full-half rate, and 18 mW/ch/Gbps at 2.67 Gbps. Each link has linear equalization, 15 deemphasis and 8 output-swing control settings, and latency of 8UI in Rx and 14-16UI in Tx. |
| doi_str_mv | 10.1109/VLSIC.2008.4586006 |
| format | Conference Proceeding |
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Individual links run at BER of 1E-12 on FR4 PCBs at 4.08-0.5 Gbps full-half rate, and 18 mW/ch/Gbps at 2.67 Gbps. Each link has linear equalization, 15 deemphasis and 8 output-swing control settings, and latency of 8UI in Rx and 14-16UI in Tx.</abstract><pub>IEEE</pub><doi>10.1109/VLSIC.2008.4586006</doi><tpages>2</tpages></addata></record> |
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| identifier | ISSN: 2158-5601 |
| ispartof | 2008 IEEE Symposium on VLSI Circuits, 2008, p.200-201 |
| issn | 2158-5601 2158-5636 |
| language | eng |
| recordid | cdi_ieee_primary_4586006 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Adaptive systems Clocks Equalizers Phase locked loops Receivers Throughput Transceivers |
| title | A teraBit/s-throughput, SerDes-based interface for a third-generation 16 core 32 thread chip-multithreading SPARC processor |
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