Compiling parallel applications to Coarse-Grained Reconfigurable Architectures
In this paper a novel approach for compiling parallel applications to a target coarse-grained reconfigurable architecture (CGRA) is presented. We have given a formal definition of the compilation problem for the CGRA. The application will be written in HARPO/L, a parallel object oriented language su...
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| creator | Tuhin, Mohammed Ashraful Alam Norvell, Theodore S. |
| description | In this paper a novel approach for compiling parallel applications to a target coarse-grained reconfigurable architecture (CGRA) is presented. We have given a formal definition of the compilation problem for the CGRA. The application will be written in HARPO/L, a parallel object oriented language suitable for hardware. HARPO/L is first compiled to a data flow graph (DFG) representation. The remaining compilation steps are a combination of three tasks: scheduling, placement and routing. For compiling cyclic portions of the application, we have adapted a modulo scheduling algorithm: modulo scheduling with integrated register spilling. For scheduling, the nodes of the DFG are ordered using the hypernode reduction modulo scheduling (HRMS) method. The placement and routing is done using the neighborhood relations of the PEs. |
| doi_str_mv | 10.1109/CCECE.2008.4564838 |
| format | Conference Proceeding |
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The placement and routing is done using the neighborhood relations of the PEs.</description><subject>Application software</subject><subject>Coarse-grained Reconfigurable Architecture</subject><subject>Computer architecture</subject><subject>Field programmable gate arrays</subject><subject>Graph Homeomorphism</subject><subject>Hardware</subject><subject>Modulo Scheduling</subject><subject>Processor scheduling</subject><subject>Programmable logic arrays</subject><subject>Reconfigurable architectures</subject><subject>Registers</subject><subject>Routing</subject><subject>Routing Resource Graph</subject><subject>Scheduling algorithm</subject><subject>Static Token</subject><issn>0840-7789</issn><issn>2576-7046</issn><isbn>9781424416424</isbn><isbn>1424416426</isbn><isbn>9781424416431</isbn><isbn>1424416434</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2008</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpVkL1OwzAURs2fRCl9AVjyAim2c69_xspqC1IFEoK5cs11MXKTyEkH3h4kujB9w9E5w8fYneBzIbh9cG7plnPJuZkDKjCNOWMzq40ACSAUNOKcTSRqVWsO6uIfk3DJJtwAr7U29prdDMMX5xyMggl7dt2hTzm1-6r3xedMufJ9n1PwY-raoRq7ynW-DFSvi08tfVSvFLo2pv2x-F2malHCZxopjMdCwy27ij4PNDvtlL2vlm_usd68rJ_cYlMn0YCprVSBMKAVAbUkwJ2V1oqIxkStEHUwAiFGC4IHNFFY-ysY3CkU5NE3U3b_101EtO1LOvjyvT1d0_wAk29TNw</recordid><startdate>200805</startdate><enddate>200805</enddate><creator>Tuhin, Mohammed Ashraful Alam</creator><creator>Norvell, Theodore S.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>200805</creationdate><title>Compiling parallel applications to Coarse-Grained Reconfigurable Architectures</title><author>Tuhin, Mohammed Ashraful Alam ; Norvell, Theodore S.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i1348-926ce5c591c572e45b92991f588f76557c8154ff9410c58f1996ce85b651ea5a3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2008</creationdate><topic>Application software</topic><topic>Coarse-grained Reconfigurable Architecture</topic><topic>Computer architecture</topic><topic>Field programmable gate arrays</topic><topic>Graph Homeomorphism</topic><topic>Hardware</topic><topic>Modulo Scheduling</topic><topic>Processor scheduling</topic><topic>Programmable logic arrays</topic><topic>Reconfigurable architectures</topic><topic>Registers</topic><topic>Routing</topic><topic>Routing Resource Graph</topic><topic>Scheduling algorithm</topic><topic>Static Token</topic><toplevel>online_resources</toplevel><creatorcontrib>Tuhin, Mohammed Ashraful Alam</creatorcontrib><creatorcontrib>Norvell, Theodore S.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Tuhin, Mohammed Ashraful Alam</au><au>Norvell, Theodore S.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Compiling parallel applications to Coarse-Grained Reconfigurable Architectures</atitle><btitle>2008 Canadian Conference on Electrical and Computer Engineering</btitle><stitle>CCECE</stitle><date>2008-05</date><risdate>2008</risdate><spage>001723</spage><epage>001728</epage><pages>001723-001728</pages><issn>0840-7789</issn><eissn>2576-7046</eissn><isbn>9781424416424</isbn><isbn>1424416426</isbn><eisbn>9781424416431</eisbn><eisbn>1424416434</eisbn><abstract>In this paper a novel approach for compiling parallel applications to a target coarse-grained reconfigurable architecture (CGRA) is presented. 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| identifier | ISSN: 0840-7789 |
| ispartof | 2008 Canadian Conference on Electrical and Computer Engineering, 2008, p.001723-001728 |
| issn | 0840-7789 2576-7046 |
| language | eng |
| recordid | cdi_ieee_primary_4564838 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Application software Coarse-grained Reconfigurable Architecture Computer architecture Field programmable gate arrays Graph Homeomorphism Hardware Modulo Scheduling Processor scheduling Programmable logic arrays Reconfigurable architectures Registers Routing Routing Resource Graph Scheduling algorithm Static Token |
| title | Compiling parallel applications to Coarse-Grained Reconfigurable Architectures |
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