On-chip at-speed linearity testing of high-resolution high-speed DACs using DDEM ADCs with dithering

On-chip testing of high-resolution high-speed DACs is extremely challenging because of the stringent requirements on the accuracy, speed and cost of the measurement circuits. This work proposed a new on-chip strategy for DAC linearity testing applying the proposed deterministic dynamic element match...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Hanqing Xing, Degang Chen, Geiger, R.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Automatic testing BIST Built-in self-test Circuit simulation Circuit testing Costs DAC linearity DDEM Digital-analog conversion Linearity Manufacturing On-chip Signal processing algorithms Velocity measurement
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