Through silicon vias technology for CMOS image sensors packaging

In this paper a low temperature 'via-last' technology will be presented. This technology has been especially developed for CMOS image sensors wafer level packaging. The design rules of the vias will be briefly described and then, the steps of the technology will be presented : glass wafer carrier bonding onto the silicon substrate, silicon thinning and backside technology including specific steps like double side lithography, silicon deep etching, silicon side wall insulation, vias metallization and final bumping. Morphological and electrical characterizations of the vias-last technology will be showed and discussed. Finally, a picture obtained with the TSV CMOS Image Sensor (TSV CIS) will be presented.