A VLSI Architecture Suitable for Mid-Level Image Processing
Despite the constant research in this field in the last 40 years, computer vision still remains as a very challenging task. Computer vision techniques used to be categorized into levels, according to the amount of cognition embodied and the output provided. Taking into account the 3-levels approach,...
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| creator | Dessbesell, G.F. Pacheco, M.A. dos S. Martins, J.B. Molz, R.F. |
| description | Despite the constant research in this field in the last 40 years, computer vision still remains as a very challenging task. Computer vision techniques used to be categorized into levels, according to the amount of cognition embodied and the output provided. Taking into account the 3-levels approach, the goal of this work is the development of a VLSI architecture suitable for mid-level processing tasks. A software evaluation has been followed by its hardware equivalent implementation. The resulting architecture takes 11,165 logic elements and proved to be around 2.5 times faster than its software counterpart. |
| doi_str_mv | 10.1109/SPL.2008.4547737 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_4547737</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>4547737</ieee_id><sourcerecordid>4547737</sourcerecordid><originalsourceid>FETCH-LOGICAL-i175t-723da8f16386c3780d44cb4dbf306996d668c0ea84adbb514cc0b41d7cc66a193</originalsourceid><addsrcrecordid>eNotj0tLw0AURgekoK3dC27mDyTOzdzMA1ehqA1ELETdlnnc1JHUSpIK_nsL9tucxYEDH2M3IHIAYe_aTZMXQpgcS9Ra6gs2BywQwdoCZmx-ctqilCVcsuU4forTpC0t4BW7r_h709a8GsJHmihMx4F4e0yT8z3x7jDw5xSzhn6o5_Xe7YhvhkOgcUxfu2s261w_0vLMBXt7fHhdrbPm5aleVU2WQJdTpgsZnelASaOC1EZExOAx-k4KZa2KSpkgyBl00fsSMAThEaIOQSkHVi7Y7X83EdH2e0h7N_xuz2flH1G-Rpw</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>A VLSI Architecture Suitable for Mid-Level Image Processing</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Dessbesell, G.F. ; Pacheco, M.A. ; dos S. Martins, J.B. ; Molz, R.F.</creator><creatorcontrib>Dessbesell, G.F. ; Pacheco, M.A. ; dos S. Martins, J.B. ; Molz, R.F.</creatorcontrib><description>Despite the constant research in this field in the last 40 years, computer vision still remains as a very challenging task. Computer vision techniques used to be categorized into levels, according to the amount of cognition embodied and the output provided. Taking into account the 3-levels approach, the goal of this work is the development of a VLSI architecture suitable for mid-level processing tasks. A software evaluation has been followed by its hardware equivalent implementation. The resulting architecture takes 11,165 logic elements and proved to be around 2.5 times faster than its software counterpart.</description><identifier>ISBN: 1424419921</identifier><identifier>ISBN: 9781424419920</identifier><identifier>DOI: 10.1109/SPL.2008.4547737</identifier><identifier>LCCN: 2007943351</identifier><language>eng</language><publisher>IEEE</publisher><subject>Character recognition ; Cognition ; Computer architecture ; Computer vision ; Image processing ; Informatics ; Labeling ; Licenses ; Pattern recognition ; Very large scale integration</subject><ispartof>2008 4th Southern Conference on Programmable Logic, 2008, p.87-92</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4547737$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4547737$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Dessbesell, G.F.</creatorcontrib><creatorcontrib>Pacheco, M.A.</creatorcontrib><creatorcontrib>dos S. Martins, J.B.</creatorcontrib><creatorcontrib>Molz, R.F.</creatorcontrib><title>A VLSI Architecture Suitable for Mid-Level Image Processing</title><title>2008 4th Southern Conference on Programmable Logic</title><addtitle>SPL</addtitle><description>Despite the constant research in this field in the last 40 years, computer vision still remains as a very challenging task. Computer vision techniques used to be categorized into levels, according to the amount of cognition embodied and the output provided. Taking into account the 3-levels approach, the goal of this work is the development of a VLSI architecture suitable for mid-level processing tasks. A software evaluation has been followed by its hardware equivalent implementation. The resulting architecture takes 11,165 logic elements and proved to be around 2.5 times faster than its software counterpart.</description><subject>Character recognition</subject><subject>Cognition</subject><subject>Computer architecture</subject><subject>Computer vision</subject><subject>Image processing</subject><subject>Informatics</subject><subject>Labeling</subject><subject>Licenses</subject><subject>Pattern recognition</subject><subject>Very large scale integration</subject><isbn>1424419921</isbn><isbn>9781424419920</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2008</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotj0tLw0AURgekoK3dC27mDyTOzdzMA1ehqA1ELETdlnnc1JHUSpIK_nsL9tucxYEDH2M3IHIAYe_aTZMXQpgcS9Ra6gs2BywQwdoCZmx-ctqilCVcsuU4forTpC0t4BW7r_h709a8GsJHmihMx4F4e0yT8z3x7jDw5xSzhn6o5_Xe7YhvhkOgcUxfu2s261w_0vLMBXt7fHhdrbPm5aleVU2WQJdTpgsZnelASaOC1EZExOAx-k4KZa2KSpkgyBl00fsSMAThEaIOQSkHVi7Y7X83EdH2e0h7N_xuz2flH1G-Rpw</recordid><startdate>200803</startdate><enddate>200803</enddate><creator>Dessbesell, G.F.</creator><creator>Pacheco, M.A.</creator><creator>dos S. Martins, J.B.</creator><creator>Molz, R.F.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200803</creationdate><title>A VLSI Architecture Suitable for Mid-Level Image Processing</title><author>Dessbesell, G.F. ; Pacheco, M.A. ; dos S. Martins, J.B. ; Molz, R.F.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-723da8f16386c3780d44cb4dbf306996d668c0ea84adbb514cc0b41d7cc66a193</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2008</creationdate><topic>Character recognition</topic><topic>Cognition</topic><topic>Computer architecture</topic><topic>Computer vision</topic><topic>Image processing</topic><topic>Informatics</topic><topic>Labeling</topic><topic>Licenses</topic><topic>Pattern recognition</topic><topic>Very large scale integration</topic><toplevel>online_resources</toplevel><creatorcontrib>Dessbesell, G.F.</creatorcontrib><creatorcontrib>Pacheco, M.A.</creatorcontrib><creatorcontrib>dos S. Martins, J.B.</creatorcontrib><creatorcontrib>Molz, R.F.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Dessbesell, G.F.</au><au>Pacheco, M.A.</au><au>dos S. Martins, J.B.</au><au>Molz, R.F.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A VLSI Architecture Suitable for Mid-Level Image Processing</atitle><btitle>2008 4th Southern Conference on Programmable Logic</btitle><stitle>SPL</stitle><date>2008-03</date><risdate>2008</risdate><spage>87</spage><epage>92</epage><pages>87-92</pages><isbn>1424419921</isbn><isbn>9781424419920</isbn><abstract>Despite the constant research in this field in the last 40 years, computer vision still remains as a very challenging task. Computer vision techniques used to be categorized into levels, according to the amount of cognition embodied and the output provided. Taking into account the 3-levels approach, the goal of this work is the development of a VLSI architecture suitable for mid-level processing tasks. A software evaluation has been followed by its hardware equivalent implementation. The resulting architecture takes 11,165 logic elements and proved to be around 2.5 times faster than its software counterpart.</abstract><pub>IEEE</pub><doi>10.1109/SPL.2008.4547737</doi><tpages>6</tpages></addata></record> |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Character recognition Cognition Computer architecture Computer vision Image processing Informatics Labeling Licenses Pattern recognition Very large scale integration |
| title | A VLSI Architecture Suitable for Mid-Level Image Processing |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-05T04%3A04%3A08IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=A%20VLSI%20Architecture%20Suitable%20for%20Mid-Level%20Image%20Processing&rft.btitle=2008%204th%20Southern%20Conference%20on%20Programmable%20Logic&rft.au=Dessbesell,%20G.F.&rft.date=2008-03&rft.spage=87&rft.epage=92&rft.pages=87-92&rft.isbn=1424419921&rft.isbn_list=9781424419920&rft_id=info:doi/10.1109/SPL.2008.4547737&rft_dat=%3Cieee_6IE%3E4547737%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=4547737&rfr_iscdi=true |