Performance analysis of IEEE defined LDPC codes under various decoding algorithms and their implementation on a reconfigurable instruction cell architecture
This paper builds a real time Programmable LDPC Decoder for decoding codes specified in IEEE 802.16 standard and discusses their performance under various decoding algorithms. Out of the decoding algorithms, the modified Min-Sum SPA is selected for implementation and optimization on a reconfigurable...
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| creator | Khan, Zahid Arslan, Tughrul Erdogan, Ahmet T. Khawam, Sami Nousias, Ioannis Milward, Mark Ying Yi |
| description | This paper builds a real time Programmable LDPC Decoder for decoding codes specified in IEEE 802.16 standard and discusses their performance under various decoding algorithms. Out of the decoding algorithms, the modified Min-Sum SPA is selected for implementation and optimization on a reconfigurable instruction cell architecture. Different general and architecture specific optimization techniques are applied to enhance the throughput. With the architecture, a throughput of 20 Mbps has been achieved. |
| doi_str_mv | 10.1109/SOCC.2007.4545443 |
| format | Conference Proceeding |
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| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 2164-1676 |
| ispartof | 2007 IEEE International SOC Conference, 2007, p.131-134 |
| issn | 2164-1676 2164-1706 |
| language | eng |
| recordid | cdi_ieee_primary_4545443 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Application specific integrated circuits Computer architecture Digital signal processing Equations Field programmable gate arrays Iterative decoding Parity check codes Performance analysis Throughput Virtual colonoscopy |
| title | Performance analysis of IEEE defined LDPC codes under various decoding algorithms and their implementation on a reconfigurable instruction cell architecture |
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