A 52mW 0.56mm2 1.2V 12b 120MS/s SHA-Free dual-channel Nyquist ADC based on mid-code calibration
This work describes a 12b 120MS/s dual-channel SHA-free Nyquist ADC based on a mid-code calibration technique eliminating offset mismatch between channels. The prototype ADC achieves a peak SNDR of 61.1dB and a peak SFDR of 74.7dB for input frequencies up to 60MHz at 120MS/s. Also, the measured DNL...
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| creator | Hee-Cheol Choi Young-Ju Kim Se-Won Lee Jae-Yeol Han Oh-Bong Kwon Younglok Kim Seung-Hoon Lee |
| description | This work describes a 12b 120MS/s dual-channel SHA-free Nyquist ADC based on a mid-code calibration technique eliminating offset mismatch between channels. The prototype ADC achieves a peak SNDR of 61.1dB and a peak SFDR of 74.7dB for input frequencies up to 60MHz at 120MS/s. Also, the measured DNL and INL are within ±0.30LSB and ±0.95LSB, respectively. The ADC fabricated in a 0.13μm CMOS process occupies an active die area of 0.56mm 2 and consumes 51.6mW. |
| doi_str_mv | 10.1109/ISCAS.2008.4541341 |
| format | Conference Proceeding |
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The prototype ADC achieves a peak SNDR of 61.1dB and a peak SFDR of 74.7dB for input frequencies up to 60MHz at 120MS/s. Also, the measured DNL and INL are within ±0.30LSB and ±0.95LSB, respectively. The ADC fabricated in a 0.13μm CMOS process occupies an active die area of 0.56mm 2 and consumes 51.6mW.</abstract><pub>IEEE</pub><doi>10.1109/ISCAS.2008.4541341</doi></addata></record> |
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| identifier | ISSN: 0271-4302 |
| ispartof | 2008 IEEE International Symposium on Circuits and Systems (ISCAS), 2008, p.9-12 |
| issn | 0271-4302 2158-1525 |
| language | eng |
| recordid | cdi_ieee_primary_4541341 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Calibration Clocks Computational Intelligence Society Design engineering Frequency Pipelines Prototypes Sampling methods Signal resolution Signal sampling |
| title | A 52mW 0.56mm2 1.2V 12b 120MS/s SHA-Free dual-channel Nyquist ADC based on mid-code calibration |
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