A 52mW 0.56mm2 1.2V 12b 120MS/s SHA-Free dual-channel Nyquist ADC based on mid-code calibration

This work describes a 12b 120MS/s dual-channel SHA-free Nyquist ADC based on a mid-code calibration technique eliminating offset mismatch between channels. The prototype ADC achieves a peak SNDR of 61.1dB and a peak SFDR of 74.7dB for input frequencies up to 60MHz at 120MS/s. Also, the measured DNL and INL are within ±0.30LSB and ±0.95LSB, respectively. The ADC fabricated in a 0.13μm CMOS process occupies an active die area of 0.56mm 2 and consumes 51.6mW.