A Study of Slow Erasing Speed at Edge Cell in Nano-Scale NAND Flash Memory

A Study of Slow Erasing Speed at Edge Cell in Nano-Scale NAND Flash Memory

In this paper, we present our study of a method to improve nonuniform erasing speeds caused by slow edge cells (cell 0 and cell 31). Simulation and measurement results showed that the slow erasing speed at edge cells is resulted from the coupling effect of select gate (SG) transistors. Moreover, sev...

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Hauptverfasser: Hsin-Heng Wang, Chiu-Tsung Huang, Shin-Hsien Chen, Kuo, R., Sophia Liu, Ling-Kuey Yang, Houng-Chi Wei, Pittikoun, S., Shirota, R., Chin-chen Cho
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Circuit testing
Costs
Electrostatic measurements
Flash memory
Manufacturing
Nonvolatile memory
Parasitic capacitance
Semiconductor device noise
Velocity measurement
Voltage
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creator Hsin-Heng Wang
Chiu-Tsung Huang
Shin-Hsien Chen
Kuo, R.
Sophia Liu
Ling-Kuey Yang
Houng-Chi Wei
Pittikoun, S.
Shirota, R.
Chin-chen Cho
description In this paper, we present our study of a method to improve nonuniform erasing speeds caused by slow edge cells (cell 0 and cell 31). Simulation and measurement results showed that the slow erasing speed at edge cells is resulted from the coupling effect of select gate (SG) transistors. Moreover, several extra bias voltages were forced on the pass wordlines to evaluate the electrostatic potential difference and to improve erase uniformity. Simulation result and measurement data demonstrated that 0.4 V of the extra bias voltage can improve the uniformity of the erasing speed in nano-scale NAND flash memory.
doi_str_mv 10.1109/VTSA.2008.4530811
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subjects Circuit testing
Costs
Electrostatic measurements
Flash memory
Manufacturing
Nonvolatile memory
Parasitic capacitance
Semiconductor device noise
Velocity measurement
Voltage
title A Study of Slow Erasing Speed at Edge Cell in Nano-Scale NAND Flash Memory
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