A Fractional Spur-Free ADPLL with Loop-Gain Calibration and Phase-Noise Cancellation for GSM/GPRS/EDGE

This paper presents a 3.2-to-4GHz fractional spur-free ADPLL. The ADPLL is fabricated in a 0.13 mum CMOS process and packaged in QFN76. Fractional spurs are filtered by accurate digital loop-gain calibration and digital phase-noise cancellation. The ADPLL is designed to minimize the switching noise...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Chang, Hsiang-Hui, Wang, Ping-Ying, Zhan, Jing-Hong Conan, Hsieh, Bing-Yu
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	1f noise Calibration Capacitors Digital control Digital filters Feedforward systems Frequency Ground penetrating radar GSM Noise cancellation
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