Automatic Optimization Techniques for Formal Verification of Asynchronous Circuits
Even medium size asynchronous circuits may display a complex behavior, due to the combinational explosion in the chronology of events that may happen. It is thus essential to apply automatic optimization techniques to avoid such complexity when formally verifying the correctness of the circuit. This...
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| creator | Boubekeur, M. Schellekens, M.P. |
| description | Even medium size asynchronous circuits may display a complex behavior, due to the combinational explosion in the chronology of events that may happen. It is thus essential to apply automatic optimization techniques to avoid such complexity when formally verifying the correctness of the circuit. This paper presents dedicated techniques for optimization of formal verification of asynchronous circuits, these include for instance: automata reduction, pre-order reduction and automatic abstraction. All these techniques have been implemented and tested in a formal verification environment. |
| doi_str_mv | 10.1109/ICECS.2007.4510985 |
| format | Conference Proceeding |
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It is thus essential to apply automatic optimization techniques to avoid such complexity when formally verifying the correctness of the circuit. This paper presents dedicated techniques for optimization of formal verification of asynchronous circuits, these include for instance: automata reduction, pre-order reduction and automatic abstraction. All these techniques have been implemented and tested in a formal verification environment.</abstract><pub>IEEE</pub><doi>10.1109/ICECS.2007.4510985</doi><tpages>4</tpages></addata></record> |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Asynchronous circuits Automata Circuit synthesis Circuit testing Cogeneration Computer displays Computer science Explosions Formal verification Interleaved codes |
| title | Automatic Optimization Techniques for Formal Verification of Asynchronous Circuits |
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