Structural DfT Approach on Folded ADCs
This paper presents a structural design for test approach for folding and interpolated analog-to-digital converters. In this methodology relative deviations between internal ADC nodes are measured to detect the presence of a fault. A behavioral model of the ADC and the DfT has been done in MATLAB/SI...
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| creator | Mozuelos, R. Lechuga, Y. Martinez, M. Bracho, S. |
| description | This paper presents a structural design for test approach for folding and interpolated analog-to-digital converters. In this methodology relative deviations between internal ADC nodes are measured to detect the presence of a fault. A behavioral model of the ADC and the DfT has been done in MATLAB/SIMULINK environment to evaluate the efficiency of the proposed test approach compared to a functional test. |
| doi_str_mv | 10.1109/ICECS.2007.4510971 |
| format | Conference Proceeding |
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In this methodology relative deviations between internal ADC nodes are measured to detect the presence of a fault. A behavioral model of the ADC and the DfT has been done in MATLAB/SIMULINK environment to evaluate the efficiency of the proposed test approach compared to a functional test.</description><identifier>ISBN: 142441377X</identifier><identifier>ISBN: 9781424413775</identifier><identifier>EISBN: 1424413788</identifier><identifier>EISBN: 9781424413782</identifier><identifier>DOI: 10.1109/ICECS.2007.4510971</identifier><identifier>LCCN: 2007928620</identifier><language>eng</language><publisher>IEEE</publisher><subject>Analog-digital conversion ; Circuit faults ; Circuit testing ; Design for testability ; Energy consumption ; Mathematical model ; MATLAB ; Microelectronics ; Performance evaluation ; Systems engineering and theory</subject><ispartof>2007 14th IEEE International Conference on Electronics, Circuits and Systems, 2007, p.226-229</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4510971$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4510971$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Mozuelos, R.</creatorcontrib><creatorcontrib>Lechuga, Y.</creatorcontrib><creatorcontrib>Martinez, M.</creatorcontrib><creatorcontrib>Bracho, S.</creatorcontrib><title>Structural DfT Approach on Folded ADCs</title><title>2007 14th IEEE International Conference on Electronics, Circuits and Systems</title><addtitle>ICECS</addtitle><description>This paper presents a structural design for test approach for folding and interpolated analog-to-digital converters. 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In this methodology relative deviations between internal ADC nodes are measured to detect the presence of a fault. A behavioral model of the ADC and the DfT has been done in MATLAB/SIMULINK environment to evaluate the efficiency of the proposed test approach compared to a functional test.</abstract><pub>IEEE</pub><doi>10.1109/ICECS.2007.4510971</doi><tpages>4</tpages></addata></record> |
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| subjects | Analog-digital conversion Circuit faults Circuit testing Design for testability Energy consumption Mathematical model MATLAB Microelectronics Performance evaluation Systems engineering and theory |
| title | Structural DfT Approach on Folded ADCs |
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