Static Frequency Divider with Enhanced Frequency Performance
This paper presents the design and measured results of a novel static frequency divider that operates at a frequency 28% higher than a current-mode logic (CML) divider. The frequency divider was designed and implemented in IBM's 0.5 μm SiGe BiCMOS technology with an f T of 47 GHz. The divider a...
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| creator | Upadhyaya, Prasanna la Rue, George S. |
| description | This paper presents the design and measured results of a novel static frequency divider that operates at a frequency 28% higher than a current-mode logic (CML) divider. The frequency divider was designed and implemented in IBM's 0.5 μm SiGe BiCMOS technology with an f T of 47 GHz. The divider adds an additional delayed clock phase to a conventional CML- based divider. Measured results show operation up to 26 GHz with power dissipation of 59 mW compared to a CML divider that operates up to 20.4 GHz with power dissipation of 54.6 mW. |
| doi_str_mv | 10.1109/WMED.2008.4510658 |
| format | Conference Proceeding |
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The frequency divider was designed and implemented in IBM's 0.5 μm SiGe BiCMOS technology with an f T of 47 GHz. The divider adds an additional delayed clock phase to a conventional CML- based divider. Measured results show operation up to 26 GHz with power dissipation of 59 mW compared to a CML divider that operates up to 20.4 GHz with power dissipation of 54.6 mW.</description><subject>Added delay</subject><subject>BiCMOS integrated circuits</subject><subject>Clocks</subject><subject>Current measurement</subject><subject>Current mode logic</subject><subject>Frequency conversion</subject><subject>Frequency measurement</subject><subject>Germanium silicon alloys</subject><subject>high-speed</subject><subject>Logic design</subject><subject>Power dissipation</subject><subject>Silicon germanium</subject><subject>static frequency divider</subject><issn>1947-3834</issn><issn>1947-3842</issn><isbn>1424423430</isbn><isbn>9781424423439</isbn><isbn>1424423449</isbn><isbn>9781424423446</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2008</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpNkNtKAzEUReOlYFv7AeLL_MCMuZxkEvBF2mkrVBQs-FgyyQmN2FEzo9K_t8WiPm3YC9aGTcgFowVj1Fw93VWTglOqC5CMKqmPyIABB-ACwByTPjNQ5kIDP_kDgp7-AgE9MtgLDOVawhkZte0zpZRxrXhp-uT6sbNddNk04fsHNm6bTeJn9Jiyr9its6pZ28ah_8cfMIXXtNnX56QX7EuLo0MOyXJaLcfzfHE_ux3fLPLIStnl3nlAbZxiQvJaSiUCome7kgZfo6qdDjagVLZGKGXNnHK7TRVEGaRSYkguf7QREVdvKW5s2q4Oj4hvcPdPjA</recordid><startdate>200804</startdate><enddate>200804</enddate><creator>Upadhyaya, Prasanna</creator><creator>la Rue, George S.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200804</creationdate><title>Static Frequency Divider with Enhanced Frequency Performance</title><author>Upadhyaya, Prasanna ; la Rue, George S.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-dcd4e89c61352b5563feed1d4e0fdbe6bc8fafe56abe475b1c6cced6f37f5663</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2008</creationdate><topic>Added delay</topic><topic>BiCMOS integrated circuits</topic><topic>Clocks</topic><topic>Current measurement</topic><topic>Current mode logic</topic><topic>Frequency conversion</topic><topic>Frequency measurement</topic><topic>Germanium silicon alloys</topic><topic>high-speed</topic><topic>Logic design</topic><topic>Power dissipation</topic><topic>Silicon germanium</topic><topic>static frequency divider</topic><toplevel>online_resources</toplevel><creatorcontrib>Upadhyaya, Prasanna</creatorcontrib><creatorcontrib>la Rue, George S.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Upadhyaya, Prasanna</au><au>la Rue, George S.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Static Frequency Divider with Enhanced Frequency Performance</atitle><btitle>2008 IEEE Workshop on Microelectronics and Electron Devices</btitle><stitle>WMED</stitle><date>2008-04</date><risdate>2008</risdate><spage>20</spage><epage>21</epage><pages>20-21</pages><issn>1947-3834</issn><eissn>1947-3842</eissn><isbn>1424423430</isbn><isbn>9781424423439</isbn><eisbn>1424423449</eisbn><eisbn>9781424423446</eisbn><abstract>This paper presents the design and measured results of a novel static frequency divider that operates at a frequency 28% higher than a current-mode logic (CML) divider. The frequency divider was designed and implemented in IBM's 0.5 μm SiGe BiCMOS technology with an f T of 47 GHz. The divider adds an additional delayed clock phase to a conventional CML- based divider. Measured results show operation up to 26 GHz with power dissipation of 59 mW compared to a CML divider that operates up to 20.4 GHz with power dissipation of 54.6 mW.</abstract><pub>IEEE</pub><doi>10.1109/WMED.2008.4510658</doi><tpages>2</tpages></addata></record> |
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| identifier | ISSN: 1947-3834 |
| ispartof | 2008 IEEE Workshop on Microelectronics and Electron Devices, 2008, p.20-21 |
| issn | 1947-3834 1947-3842 |
| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Added delay BiCMOS integrated circuits Clocks Current measurement Current mode logic Frequency conversion Frequency measurement Germanium silicon alloys high-speed Logic design Power dissipation Silicon germanium static frequency divider |
| title | Static Frequency Divider with Enhanced Frequency Performance |
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