Failure Mode Detection and Process Optimization for 65 nm CMOS Technology
Short loop test flows have been commonly used in back end of line (BEOL) interconnect process development to speed up learning rates and improve yields. This paper presents case studies on the expanded use of short loop test chips to the shallow trench isolation (STI), gate and pre- metal dielectric...
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| creator | DeBord, J.R.D. Olsen, L. Jin Zhao Bonifield, T. Lytle, S. |
| description | Short loop test flows have been commonly used in back end of line (BEOL) interconnect process development to speed up learning rates and improve yields. This paper presents case studies on the expanded use of short loop test chips to the shallow trench isolation (STI), gate and pre- metal dielectric (PMD)Z contact loops of a 65 nm process technology in addition to the BEOL. These test chips have been used to quickly identify and eliminate random and systematic defect mechanisms and generate a robust process flow, thus accelerating the rate of yield learning. |
| doi_str_mv | 10.1109/ISSM.2006.4493011 |
| format | Conference Proceeding |
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| subjects | Acceleration CMOS process CMOS technology Contacts Dielectric materials Failure analysis Isolation technology Life estimation Random access memory System testing |
| title | Failure Mode Detection and Process Optimization for 65 nm CMOS Technology |
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