Physical Implementation of the DSPIN Network-on-Chip in the FAUST Architecture

This paper presents a physical implementation of the DSPIN network-on-chip in the FAUST architecture. FAUST is a stream-oriented multi- application SoC platform for telecommunications addressing IEEE 802.11a and MC-CDMA standards. The original asynchronous network-on-chip (ANOC) of FAUST has been re...

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Bibliographische Detailangaben
Hauptverfasser:	Miro-Panades, I., Clermidy, F., Vivet, P., Greiner, A.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	ANOC bi-synchronous FIFO Clocks CMOS process Computer Science Delay DSPIN Energy consumption FAUST Frequency Memory architecture Multicarrier code division multiple access Network-on-a-chip network-on-chip NoC physical implementation Telecommunication standards Throughput
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