A new scheduling algorithm for processor-based logic emulation systems
In this paper a design compilation CAD tool suite, that maps gate-level netlists of design-under-test (DUT) into a specific class of processor-based logic emulation systems, is presented. The application of static scheduling algorithms and their effect on logic emulation time is discussed. A variati...
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| creator | Yazdanshenas, A. Khalid, M.A.S. |
| description | In this paper a design compilation CAD tool suite, that maps gate-level netlists of design-under-test (DUT) into a specific class of processor-based logic emulation systems, is presented. The application of static scheduling algorithms and their effect on logic emulation time is discussed. A variation of static scheduling algorithm, and its enhancement, are introduced and results on ten MCNC benchmark circuits are presented and compared. Our results show that both algorithms result in an average processor workload of more than 83% while keeping processor idle time close to minimal. Also, the execution speed-up achieved by both algorithms, on average, is 50 times faster than sequential execution of emulation program. |
| doi_str_mv | 10.1109/MWSCAS.2007.4488826 |
| format | Conference Proceeding |
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Also, the execution speed-up achieved by both algorithms, on average, is 50 times faster than sequential execution of emulation program.</description><subject>Design automation</subject><subject>Emulation</subject><subject>Field programmable gate arrays</subject><subject>Hardware</subject><subject>Logic arrays</subject><subject>Logic design</subject><subject>Logic devices</subject><subject>Logic programming</subject><subject>Processor scheduling</subject><subject>Scheduling algorithm</subject><issn>1548-3746</issn><issn>1558-3899</issn><isbn>1424411750</isbn><isbn>9781424411757</isbn><isbn>1424411769</isbn><isbn>9781424411764</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2007</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpF0N1KwzAcBfD4BW7TJ9hNXqA1adImuSzFqTDxYgMvR9L800XaZiQdsrd34sCrc_GDA-cgtKQkp5Sop_fPTVNv8oIQkXMupSyqKzSnvOCcUlGpazSjZSkzJpW6-YeS3P4CP4Pg1T2ap_RFSMEEVTO0qvEI3zi1e7DH3o8d1n0Xop_2A3Yh4kMMLaQUYmZ0Aov70PkWw3Ds9eTDiNMpTTCkB3TndJ_g8ZILtF09b5vXbP3x8tbU68wrMmUGjCwrS53ipmLAJedMSOGUtoa7UtjzMhAgDdGOKemoM9Da1mlNJHFOswVa_tV6ANgdoh90PO0uX7AfxnZRcg</recordid><startdate>200708</startdate><enddate>200708</enddate><creator>Yazdanshenas, A.</creator><creator>Khalid, M.A.S.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>200708</creationdate><title>A new scheduling algorithm for processor-based logic emulation systems</title><author>Yazdanshenas, A. ; Khalid, M.A.S.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-beb856d1f94b63e48443787f9adb4f57d007e7e8b0af398f1fbecdcfaa080ffa3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2007</creationdate><topic>Design automation</topic><topic>Emulation</topic><topic>Field programmable gate arrays</topic><topic>Hardware</topic><topic>Logic arrays</topic><topic>Logic design</topic><topic>Logic devices</topic><topic>Logic programming</topic><topic>Processor scheduling</topic><topic>Scheduling algorithm</topic><toplevel>online_resources</toplevel><creatorcontrib>Yazdanshenas, A.</creatorcontrib><creatorcontrib>Khalid, M.A.S.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Yazdanshenas, A.</au><au>Khalid, M.A.S.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A new scheduling algorithm for processor-based logic emulation systems</atitle><btitle>2007 50th Midwest Symposium on Circuits and Systems</btitle><stitle>MWSCAS</stitle><date>2007-08</date><risdate>2007</risdate><spage>1505</spage><epage>1508</epage><pages>1505-1508</pages><issn>1548-3746</issn><eissn>1558-3899</eissn><isbn>1424411750</isbn><isbn>9781424411757</isbn><eisbn>1424411769</eisbn><eisbn>9781424411764</eisbn><abstract>In this paper a design compilation CAD tool suite, that maps gate-level netlists of design-under-test (DUT) into a specific class of processor-based logic emulation systems, is presented. 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| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Design automation Emulation Field programmable gate arrays Hardware Logic arrays Logic design Logic devices Logic programming Processor scheduling Scheduling algorithm |
| title | A new scheduling algorithm for processor-based logic emulation systems |
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